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* [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov2014-07-211-1/+5
| | | | | | | | | | | | Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
* X86: expand atomics in IR instead of as MachineInstrs.Tim Northover2014-07-011-21/+0
| | | | | | | | | | | | The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
* [X86] Add support for builtin to read performance monitoring counters.Andrea Di Biagio2014-06-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a new builtin instruction called __builtin_ia32_rdpmc. Builtin '__builtin_ia32_rdpmc' is defined as a 'GCC builtin'; on X86, it can be used to read performance monitoring counters. It takes as input the index of the performance counter to read, and returns the value of the specified performance counter as a 64-bit number. Calls to this new builtin will map to instruction RDPMC. The index in input to the builtin call is moved to register %ECX. The result of the builtin call is the value of the specified performance counter (RDPMC would return that quantity in registers RDX:RAX). This patch: - Adds builtin int_x86_rdpmc as a GCCBuiltin; - Adds a new x86 DAG node called 'RDPMC_DAG'; - Teaches how to lower this new builtin; - Adds an ISel pattern to select instruction RDPMC; - Fixes the definition of instruction RDPMC adding %RAX and %RDX as implicit definitions, and adding %ECX as implicit use; - Adds a LLVM test to verify that the new builtin is correctly selected. llvm-svn: 212049
* [X86] Use ADD/SUB instead of INC/DEC for SilvermontAlexey Volkov2014-06-091-0/+1
| | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 llvm-svn: 210466
* [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.Andrea Di Biagio2014-05-191-0/+81
| | | | | | | | | | Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
* X86: disable printing of bare "mov" aliasesTim Northover2014-05-161-3/+3
| | | | | | | | | | | In AT&T syntax, we should probably print the full "movl" or "movw". TableGen used to ignore these aliases because it was miscounting the number of operands. This fixes the issue. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208963
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-151-16/+16
| | | | | | | | | | | | | | Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-12/+22
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.Andrea Di Biagio2014-04-241-0/+2
| | | | | | | | | | | | | | This patch: - Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and 'int_x86_rdtscp') as GCCBuiltin intrinsics; - Teaches the backend how to lower the two new builtins; - Introduces a common function to lower READCYCLECOUNTER dag nodes and the two new rdtsc/rdtscp intrinsics; - Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll' correctly verifies that both READCYCLECOUNTER and the two new intrinsics work fine for both 64bit and 32bit Subtargets. llvm-svn: 207127
* [X86] Require HasBMI2 for the new BZHI tablegen patterns.Lang Hames2014-04-221-20/+22
| | | | | | | Evidently tablegen doesn't infer this from the HasBMI2 predicate on the BZHI instructions. This should fix the recent bot failures. llvm-svn: 206885
* [X86] Remove Tablegen def of X86bzhi SDNode: It's not needed as of r206879.Lang Hames2014-04-221-1/+0
| | | | llvm-svn: 206880
* [X86] Use tablegen instead of DAG combines to match BZHI instructions, asLang Hames2014-04-221-12/+30
| | | | | | | | suggested by Ben Kramer in review of r206738. Thanks again Ben! llvm-svn: 206879
* [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODSCraig Topper2014-02-271-23/+49
| | | | llvm-svn: 202348
* [X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions.Craig Topper2014-02-271-0/+4
| | | | llvm-svn: 202347
* [X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move ↵Craig Topper2014-02-271-0/+20
| | | | | | instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
* Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their ↵Craig Topper2014-02-181-11/+12
| | | | | | 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-181-27/+23
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.Craig Topper2014-02-151-0/+10
| | | | llvm-svn: 201463
* [X86] Don't mark movabsq as cheap-as-move - it isn't that cheap.Juergen Ributzka2014-02-141-3/+5
| | | | | | | | | A simple register copy on X86 is just 3 bytes, whereas movabsq is a 10 byte instruction. Marking movabsq as not beeing cheap will allow LICM to move it out of the loop and it also prevents unnecessary rematerializations if the value is needed in more than one register. llvm-svn: 201377
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-2/+2
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-2/+2
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-2/+2
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns ↵Craig Topper2014-02-051-20/+34
| | | | | | instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense. llvm-svn: 200824
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-142/+144
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-4/+4
| | | | | | in TSFlags. llvm-svn: 200624
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-301-7/+8
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
* [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)David Woodhouse2014-01-221-3/+6
| | | | llvm-svn: 199808
* [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)David Woodhouse2014-01-221-8/+8
| | | | llvm-svn: 199807
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-221-5/+8
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)David Woodhouse2014-01-221-5/+20
| | | | llvm-svn: 199805
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-4/+56
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-5/+56
| | | | llvm-svn: 199803
* [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSLDavid Woodhouse2014-01-201-5/+5
| | | | | | | | The disassembler has a special case for 'L' vs. 'W' in its heuristic for checking for 32-bit and 16-bit equivalents. We could expand the heuristic, but better just to be consistent in using the 'L' suffix. llvm-svn: 199652
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-24/+28
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* [x86] Fix retq/retl handling in 64-bit modeDavid Woodhouse2014-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This finishes the job started in r198756, and creates separate opcodes for 64-bit vs. 32-bit versions of the rest of the RET instructions too. LRETL/LRETQ are interesting... I can't see any justification for their existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no need for a REX.W prefix for LRETQ. But this is what GAS does, and my Sandybridge CPU and an Opteron 6376 concur when tested as follows: asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:"); asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:"); asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to match it. I don't quite understand how the Intel syntax parsing for ret instructions is working, despite r154468 allegedly fixing it. Aren't the explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at least made the 'lretq' work with (and indeed *require*) the 'q'. llvm-svn: 199106
* [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)David Woodhouse2014-01-081-1/+4
| | | | | | | | They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. llvm-svn: 198761
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-7/+27
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-081-4/+7
| | | | | | | | | | I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-081-8/+12
| | | | llvm-svn: 198755
* [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliasesDavid Woodhouse2014-01-081-7/+22
| | | | llvm-svn: 198754
* [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit modeDavid Woodhouse2014-01-081-8/+25
| | | | llvm-svn: 198753
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-081-64/+85
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
* [x86] Add basic support for .code16Craig Topper2014-01-061-0/+6
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-051-2/+4
| | | | llvm-svn: 198547
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-051-1/+2
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-051-18/+18
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-021-1/+2
| | | | llvm-svn: 198336
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-0/+4
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-38/+38
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-2/+2
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
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