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path: root/llvm/lib/Target/X86/X86InstrInfo.cpp
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* Fix a long-standing wart in the code generator: two-address instruction loweringChris Lattner2006-09-051-1/+1
| | | | | | | | | | | | | | | actually *removes* one of the operands, instead of just assigning both operands the same register. This make reasoning about instructions unnecessarily complex, because you need to know if you are before or after register allocation to match up operand #'s with the target description file. Changing this also gets rid of a bunch of hacky code in various places. This patch also includes changes to fold loads into cmp/test instructions in the X86 backend, along with a significant simplification to the X86 spill folding code. llvm-svn: 30108
* Can't commute shufps. The high / low parts elements come from different vectors.Evan Cheng2006-07-251-18/+0
| | | | llvm-svn: 29275
* Commute shufps / shufpd.Evan Cheng2006-05-301-0/+18
| | | | llvm-svn: 28577
* Somehow I lost a condition when I was shuffling some code around. Anyway,Evan Cheng2006-05-301-1/+1
| | | | | | only transform a shufps to pshufd when the first two operands are the same. llvm-svn: 28575
* Fix a build breaker.Evan Cheng2006-05-301-10/+12
| | | | llvm-svn: 28574
* Oops. PSHUFD is only available with SSE2.Evan Cheng2006-05-301-5/+8
| | | | llvm-svn: 28573
* Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.Evan Cheng2006-05-301-1/+12
| | | | llvm-svn: 28565
* These can be transformed into lea as well. Not that we use this featureEvan Cheng2006-05-191-0/+2
| | | | | | currently... llvm-svn: 28393
* Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and ↵Evan Cheng2006-05-111-0/+4
| | | | | | isStoreToStackSlot llvm-svn: 28223
* Fixing truncate. Previously we were emitting truncate from r16 to r8 asEvan Cheng2006-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | movw. That is we promote the destination operand to r16. So %CH = TRUNC_R16_R8 %BP is emitted as movw %bp, %cx. This is incorrect. If %cl is live, it would be clobbered. Ideally we want to do the opposite, that is emitted it as movb ??, %ch But this is not possible since %bp does not have a r8 sub-register. We are now defining a new register class R16_ which is a subclass of R16 containing only those 16-bit registers that have r8 sub-registers (i.e. AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the value to the R16_ class, followed by a TRUNC_R16_R8. Due to bug 770, the register colaescer is not going to coalesce between R16 and R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it can only be eliminated if we are lucky that source and destination registers are the same. llvm-svn: 28164
* Teach the codegen about instructions used for SSE spill code, allowing itChris Lattner2006-04-181-0/+4
| | | | | | to optimize cases where it has to spill a lot llvm-svn: 27801
* - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.Evan Cheng2006-04-031-2/+4
| | | | | | - Some bug fixes and naming inconsistency fixes. llvm-svn: 27377
* Support for scalar to vector with zero extension.Evan Cheng2006-03-241-1/+2
| | | | llvm-svn: 27091
* - Remove scalar to vector pseudo ops. They are just wrong.Evan Cheng2006-03-211-1/+2
| | | | | | | - Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS and MOVAPD. Mark them as move instructions and *hope* they will be deleted. llvm-svn: 26919
* 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. ThisEvan Cheng2006-02-161-0/+1
| | | | | | | | | | | proves to be worth 20% on Ptrdist/ks. Might be related to dependency breaking support. 2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These are used for FR32 / FR64 reg-to-reg copies. 3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to spill / restore FsMOVAPSrr and FsMOVAPDrr. llvm-svn: 26241
* fix operand numbersChris Lattner2006-02-021-4/+4
| | | | llvm-svn: 25915
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-0/+48
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
* Tell codegen MOVAPSrr and MOVAPDrr are copies.Evan Cheng2006-02-011-1/+2
| | | | llvm-svn: 25889
* Properly split f32 and f64 into separate register classes for scalar sse fpNate Begeman2005-10-141-1/+1
| | | | | | fixing a bunch of nasty hackery llvm-svn: 23735
* Teach the register allocator that movaps is also a move instructionNate Begeman2005-07-161-1/+1
| | | | llvm-svn: 22451
* First round of support for doing scalar FP using the SSE2 ISA extension andNate Begeman2005-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
* * Remove trailing whitespaceMisha Brukman2005-04-211-4/+4
| | | | | | * Convert tabs to spaces llvm-svn: 21426
* When commuting these instructions, make sure to actually swap the operands too.Chris Lattner2005-01-191-1/+1
| | | | llvm-svn: 19694
* Improve coverage of the X86 instruction set by adding 16-bit shift doubles.Chris Lattner2005-01-191-3/+12
| | | | llvm-svn: 19687
* Teach the code generator that shrd/shld is commutable if it has an immediate.Chris Lattner2005-01-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
* Disable 2->3 address promotion of add and inc instructions to LEA's. InChris Lattner2005-01-021-0/+5
| | | | | | | | addition to being three address, LEA's don't set the flags. This fixes 186.crafty. llvm-svn: 19251
* Implement the convertToThreeAddress method, add support for inverting JP/JNPChris Lattner2005-01-021-0/+81
| | | | | | branches. llvm-svn: 19247
* Fix a warningChris Lattner2004-08-011-2/+1
| | | | llvm-svn: 15409
* Align breaks.Alkis Evlogimenos2004-07-311-6/+6
| | | | llvm-svn: 15371
* Add breaksChris Lattner2004-07-311-12/+12
| | | | llvm-svn: 15365
* Simplify code a bit.Alkis Evlogimenos2004-07-311-3/+1
| | | | llvm-svn: 15364
* Correctly spell 'unconditional'.Alkis Evlogimenos2004-07-311-1/+1
| | | | llvm-svn: 15363
* Implement insertGoto and reverseBranchCondition for the X86.Alkis Evlogimenos2004-07-311-0/+33
| | | | llvm-svn: 15362
* A big X86 instruction rename. The instructions are renamed to makeAlkis Evlogimenos2004-02-291-1/+1
| | | | | | | | | | | | | | | | their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
* Adjust to change in TII ctor argumentsChris Lattner2004-02-291-3/+1
| | | | llvm-svn: 11987
* These two virtual methods are never called.Chris Lattner2004-02-291-27/+0
| | | | llvm-svn: 11984
* Move MOTy::UseType enum into MachineOperand. This eliminates theAlkis Evlogimenos2004-02-221-2/+2
| | | | | | | | | switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). llvm-svn: 11715
* Remove getAllocatedRegNum(). Use getReg() instead.Alkis Evlogimenos2004-02-131-2/+2
| | | | llvm-svn: 11393
* Don't use MachineOperator::is(Phys|Virt)RegisterChris Lattner2004-02-101-2/+2
| | | | llvm-svn: 11276
* Tighten up checksChris Lattner2004-02-101-2/+2
| | | | llvm-svn: 11274
* FpMOV is also a move instruction.Alkis Evlogimenos2004-02-011-1/+2
| | | | llvm-svn: 11055
* Add TargetInstrInfo::isMoveInstr() to support coalescing in registerAlkis Evlogimenos2003-12-281-0/+15
| | | | | | allocation. llvm-svn: 10633
* Put all LLVM code into the llvm namespace, as per bug 109.Brian Gaeke2003-11-111-0/+2
| | | | llvm-svn: 9903
* Added LLVM project notice to the top of every C++ source file.John Criswell2003-10-201-0/+7
| | | | | | Header files will be on the way. llvm-svn: 9298
* * Start using tablegen'd instruction descriptionsChris Lattner2003-08-031-43/+6
| | | | | | | | * Fix bug in the createNOP method, which was not marking the operands of the generated XCHG as useanddef. I don't think this method is actually used, so it wasn't breaking anything, but it should be fixed anyway... llvm-svn: 7539
* Reword to remove reference to how things worked in the past.Misha Brukman2003-05-241-4/+3
| | | | llvm-svn: 6323
* Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.Misha Brukman2003-05-241-1/+29
| | | | llvm-svn: 6320
* Rename MachineInstrInfo -> TargetInstrInfoChris Lattner2003-01-141-3/+3
| | | | llvm-svn: 5272
* Add comments, switch uses/defs to match InstrInfo.def fileChris Lattner2002-12-181-2/+10
| | | | llvm-svn: 5102
* * Move information about Implicit Defs/Uses into X86InstrInfo.def.Chris Lattner2002-12-031-4/+10
| | | | | | | * Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. llvm-svn: 4877
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