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path: root/llvm/lib/Target/X86/X86Instr64bit.td
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* distribute the rest of the contents of X86Instr64bit.td out toChris Lattner2010-10-051-220/+0
| | | | | | the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
* move the rest of the simple 64-bit arithmetic into InstrArithmetic.tdChris Lattner2010-10-051-216/+0
| | | | llvm-svn: 115663
* continue moving 64-bit stuff into X86InstrArithmetic.tdChris Lattner2010-10-051-211/+1
| | | | llvm-svn: 115660
* move 64-bit add and adc to InstrArithmetic.Chris Lattner2010-10-051-103/+0
| | | | llvm-svn: 115632
* integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.Chris Lattner2010-10-051-221/+0
| | | | llvm-svn: 115608
* move sign and zero extensions out to their own file.Chris Lattner2010-10-051-70/+0
| | | | llvm-svn: 115605
* move some instructions from Instr64Bit -> InstrInfo.Chris Lattner2010-10-051-86/+0
| | | | | | bswap32 doesn't read eflags. llvm-svn: 115604
* move CMOV_FR32 and friends to InstrCompiler, since they are Chris Lattner2010-10-051-9/+0
| | | | | | | | pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
* move various pattern matching support goop out of X86Instr64Bit, to liveChris Lattner2010-10-051-87/+0
| | | | | | with the 32-bit stuff. llvm-svn: 115602
* split conditional moves and setcc's out to their own file.Chris Lattner2010-10-051-179/+0
| | | | llvm-svn: 115601
* move string pseudo instructions to InstrCompiler consolidate 64-bit and ↵Chris Lattner2010-10-051-17/+0
| | | | | | 32-bit together. llvm-svn: 115600
* move the atomic pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-051-153/+0
| | | | llvm-svn: 115599
* move more pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-051-51/+0
| | | | llvm-svn: 115598
* continue moving stuff out to X86InstrSystem.td. MoveChris Lattner2010-10-051-591/+0
| | | | | | | | control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
* refactor .td files a bit, moving system instructions out to X86InstrSystem.tdChris Lattner2010-10-051-32/+0
| | | | llvm-svn: 115591
* Properly emit stack probe on win64 (for non-mingw targets).Anton Korobeynikov2010-10-031-4/+4
| | | | | | Based on the patch by Cameron Esfahani! llvm-svn: 115479
* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-231-2/+2
| | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! llvm-svn: 114710
* Add isConditionalMove bits to X86 and ARM instructions.Owen Anderson2010-09-231-2/+2
| | | | llvm-svn: 114703
* Fix an inconsistency in the x86 backend that led it to reject "calll foo" onChris Lattner2010-09-221-2/+2
| | | | | | | | | | | | x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. llvm-svn: 114534
* reimplement support for GS and FS relative address space matchingChris Lattner2010-09-211-10/+0
| | | | | | | | | | | | | | | | | by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
* fix wonky formatting.Chris Lattner2010-09-081-1/+1
| | | | llvm-svn: 113426
* implement proper support for sysret{,l,q}, rdar://8403907Chris Lattner2010-09-081-0/+4
| | | | llvm-svn: 113350
* implement the iret suite of instructions properly,Chris Lattner2010-09-081-1/+2
| | | | | | fixing rdar://8403974 llvm-svn: 113349
* Don't call Predicate_* from X86 target.Jakob Stoklund Olesen2010-09-031-5/+1
| | | | llvm-svn: 112921
* X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard ↵Daniel Dunbar2010-08-271-1/+1
| | | | | | to find miscompiles with the integrated assembler. llvm-svn: 112250
* X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / ↵Daniel Dunbar2010-08-251-4/+3
| | | | | | clang -O3. llvm-svn: 112089
* Comment out some broken/unused/useless instructions which mess up disassembly.Eli Friedman2010-08-161-0/+6
| | | | llvm-svn: 111185
* Set hasSideEffects on the 64-bit no-sse memory barrier.Eric Christopher2010-08-051-1/+1
| | | | llvm-svn: 110369
* Be a little bit more specific about target for the memory barrierEric Christopher2010-08-051-1/+2
| | | | | | instructions. llvm-svn: 110360
* Make x86-64 membarriers work without sse and clean up some of theEric Christopher2010-08-041-0/+7
| | | | | | uses. llvm-svn: 110274
* fix a win64 encoding problem, patch by Cameron Esfahani!Chris Lattner2010-08-031-1/+1
| | | | llvm-svn: 110164
* Support all 128-bit AVX vector intrinsics. Most part of them I alreadyBruno Cardoso Lopes2010-07-301-110/+0
| | | | | | | | | | | declared during the addition of the assembler support, the additional changes are: - Add missing intrinsics - Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file. - Duplicate some patterns to AVX mode. - Step into PCMPEST/PCMPIST custom inserter and add AVX versions. llvm-svn: 109878
* X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the sameDaniel Dunbar2010-07-191-2/+2
| | | | | | | | instruction, we only want to allow the one for the current subtarget. - This also fixes suffix matching for jmp instructions, because it eliminates the ambiguity between 'jmpl' and 'jmpq'. llvm-svn: 108746
* X86-64: Mark WINCALL and more tail call instructions as code gen only.Daniel Dunbar2010-07-191-2/+3
| | | | llvm-svn: 108685
* X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].Daniel Dunbar2010-07-191-2/+2
| | | | llvm-svn: 108683
* X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.Daniel Dunbar2010-07-191-0/+2
| | | | llvm-svn: 108680
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-081-17/+12
| | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
* A slight reworking of the custom patterns for x86-64 tpoff codegen andEric Christopher2010-07-081-9/+11
| | | | | | | | correct the testcase for valid assembly. Needs more tests. llvm-svn: 107860
* Use only one multiclass to pinsrq instructionsBruno Cardoso Lopes2010-07-071-24/+0
| | | | llvm-svn: 107750
* Now that almost all SSE4.1 AVX instructions are added, move code around to ↵Bruno Cardoso Lopes2010-07-071-18/+0
| | | | | | more appropriate sections. No functionality changes llvm-svn: 107749
* Add a couple more quick comments.Eric Christopher2010-06-241-0/+2
| | | | llvm-svn: 106717
* Update according to feedback.Eric Christopher2010-06-231-1/+1
| | | | llvm-svn: 106677
* Update uses, defs, and comments for darwin tls patterns.Eric Christopher2010-06-231-7/+4
| | | | llvm-svn: 106621
* Add some codegen patterns for x86_64-linux-gnu tls codegen matching.Eric Christopher2010-06-211-0/+9
| | | | | | Based on a patch by Patrick Marlier! llvm-svn: 106433
* Remove isTwoAddress from 64-bit files.Eric Christopher2010-06-181-15/+15
| | | | llvm-svn: 106356
* Some assorted isTwoAddress -> Constraints cleanup.Eric Christopher2010-06-181-60/+56
| | | | llvm-svn: 106273
* Ensure that mov and not lea are used to stick the address intoEric Christopher2010-06-081-3/+3
| | | | | | the register. While we're at it, make sure it's in the right one. llvm-svn: 105645
* Add first pass at darwin tls compiler support.Eric Christopher2010-06-031-0/+13
| | | | llvm-svn: 105381
* AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expectedDaniel Dunbar2010-05-261-0/+14
| | | | | | to be matched. llvm-svn: 104757
* The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is requiredKevin Enderby2010-05-251-1/+2
| | | | | | for the 64-bit version of the Bit Test instruction. llvm-svn: 104621
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