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* Rename X86 subregister indices to something shorter.Jakob Stoklund Olesen2010-05-241-35/+35
| | | | | | Use the tablegen-produced enums. llvm-svn: 104493
* MC/X86: Subdivide immediates a bit more, so that we properly recognize ↵Daniel Dunbar2010-05-221-2/+2
| | | | | | | | | | | immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
* MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with ↵Daniel Dunbar2010-05-201-0/+7
| | | | | | movq. llvm-svn: 104275
* X86: Model i64i32imm properly, as a subclass of all immediates.Daniel Dunbar2010-05-201-1/+3
| | | | llvm-svn: 104272
* X86: Fix immediate type of FOO64i32 operations.Daniel Dunbar2010-05-201-10/+10
| | | | llvm-svn: 104271
* Fix assembly parsing and encoding of the pushf and popf family ofDan Gohman2010-05-201-2/+4
| | | | | | instructions. llvm-svn: 104231
* Set neverHasSideEffects on 64-bit pushf and popf, for consistency withDan Gohman2010-05-201-2/+2
| | | | | | 16-bit and 32-bit pushf and popf. llvm-svn: 104228
* Add mayLoad and mayStore flags to instructions which missed them.Dan Gohman2010-05-141-1/+6
| | | | llvm-svn: 103776
* fix rdar://7947167 - llvm-mc doesn't match movsqChris Lattner2010-05-061-4/+10
| | | | llvm-svn: 103199
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+2
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcodeKevin Enderby2010-05-041-1/+1
| | | | | | changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI. llvm-svn: 102991
* Fixed the encoding of two of the X86 movq instuctions. The Move quadword fromKevin Enderby2010-05-031-1/+1
| | | | | | | mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect encodings. llvm-svn: 102952
* Remove the -disable-16bit command-line option, which is now obsolete.Dan Gohman2010-04-301-12/+0
| | | | llvm-svn: 102730
* Enable i16 to i32 promotion by default.Evan Cheng2010-04-281-0/+5
| | | | llvm-svn: 102493
* Rather than having a ton of patterns for double shift instructions, e.g. ↵Evan Cheng2010-04-281-15/+0
| | | | | | SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). llvm-svn: 102485
* fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptestChris Lattner2010-03-281-6/+4
| | | | | | nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
* eliminate the last of the parallel's!Chris Lattner2010-03-271-166/+100
| | | | llvm-svn: 99700
* remove 64-bit or_is_add parallels.Chris Lattner2010-03-241-6/+3
| | | | llvm-svn: 99360
* remove the patterns that I commented out in r98930, Dan verified Chris Lattner2010-03-191-113/+0
| | | | | | that they are dead. llvm-svn: 99000
* MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen ↵Daniel Dunbar2010-03-191-8/+16
| | | | | | only" so they don't get selected by the asm matcher. llvm-svn: 98972
* comment out a bunch of parallel store patterns that apparentlyChris Lattner2010-03-191-4/+22
| | | | | | | can't match or just have no testcases. Will remove after confirmation from dan that they really are dead. llvm-svn: 98930
* X86: Fix encoding for TEST64rr.Daniel Dunbar2010-03-191-1/+1
| | | | llvm-svn: 98919
* Now that tblgen can handle matching implicit defs of instructionsChris Lattner2010-03-191-29/+21
| | | | | | | | | | | | | | | | | | | | | | | | | to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
* callq is pcrelativeChris Lattner2010-03-181-1/+1
| | | | llvm-svn: 98835
* fix the same bug on the x86-64 side of the fence.Chris Lattner2010-03-161-1/+1
| | | | llvm-svn: 98616
* Fix jit encoding bugs.Evan Cheng2010-03-141-4/+4
| | | | llvm-svn: 98510
* Do not force indirect tailcall through fixed registers: eax, r11. Add ↵Evan Cheng2010-03-141-20/+61
| | | | | | support to allow loads to be folded to tail call instructions. llvm-svn: 98465
* X86_64: Fix encoding for the rest of the 64i32 instructions too.Daniel Dunbar2010-03-131-12/+12
| | | | llvm-svn: 98458
* X86: Fix ADD64i32 encoding.Daniel Dunbar2010-03-131-2/+2
| | | | llvm-svn: 98457
* MC/X86_64: Fix matching of leaq.Daniel Dunbar2010-03-131-2/+2
| | | | llvm-svn: 98444
* MC/X86_64: Fix matching of callq.Daniel Dunbar2010-03-131-0/+1
| | | | llvm-svn: 98443
* Correct immediate sizes.Chris Lattner2010-03-081-1/+1
| | | | llvm-svn: 97957
* factor the 'sign extended from 8 bit' patterns better so Chris Lattner2010-03-031-5/+1
| | | | | | | | that they are not destination type specific. This allows tblgen to factor them and the type check is redundant with what the isel does anyway. llvm-svn: 97629
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-271-1/+1
| | | | llvm-svn: 97348
* fix an incorrect (overly conservative) predicate.Chris Lattner2010-02-271-1/+1
| | | | llvm-svn: 97316
* remove a bunch of dead named arguments in input patterns,Chris Lattner2010-02-231-10/+10
| | | | | | though some look dubious afaict, these are all ok. llvm-svn: 96899
* fix a type mismatch in this pattern, where we were using an i64 imm in a Chris Lattner2010-02-231-1/+7
| | | | | | | | place where an i32 imm was required, the old isel just got lucky. This fixes CodeGen/X86/x86-64-and-mask.ll llvm-svn: 96894
* remove special cases for vmlaunch, vmresume, vmxoff, and swapgsChris Lattner2010-02-131-1/+1
| | | | | | fix swapgs to be spelled right. llvm-svn: 96058
* X86: Fix definition for RCL/RCR.*m? operations -- they were getting representedDaniel Dunbar2010-02-121-19/+22
| | | | | | with "tied memory operands", which is wrong. llvm-svn: 95950
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-1/+1
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* really kill off the last MRMInitReg inst, remove logic from encoder.Chris Lattner2010-02-051-2/+1
| | | | llvm-svn: 95437
* factor code better in X86MCInstLower::Lower, teach it toChris Lattner2010-02-051-2/+6
| | | | | | lower the SETB* instructions. llvm-svn: 95431
* Change TAILJMP's to be varargs and transfer implicit uses over from ↵Evan Cheng2010-01-311-1/+1
| | | | | | TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. llvm-svn: 94950
* Mark EH_RETURN64 as CodeGenOnly.Daniel Dunbar2010-01-221-1/+1
| | | | llvm-svn: 94205
* Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add ↵Evan Cheng2010-01-121-3/+5
| | | | | | patterns first. llvm-svn: 93245
* Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.Dan Gohman2010-01-121-9/+13
| | | | llvm-svn: 93229
* Extend r93152 to work on OR r, r. If the source set bits are known not to ↵Evan Cheng2010-01-111-2/+5
| | | | | | overlap, then select as an ADD instead. llvm-svn: 93191
* Revert 93158. It's breaking quite a few x86_64 tests.Evan Cheng2010-01-111-11/+8
| | | | llvm-svn: 93185
* Use a 32-bit and with implicit zero-extension instead of a 64-bit and if itDan Gohman2010-01-111-0/+11
| | | | | | | | | | | has an immediate with at least 32 bits of leading zeros, to avoid needing to materialize that immediate in a register first. FileCheckize, tidy, and extend a testcase to cover this case. This fixes rdar://7527390. llvm-svn: 93160
* Re-instate MOV64r0 and MOV16r0, with adjustments to work with theDan Gohman2010-01-111-8/+11
| | | | | | | | new AsmPrinter. This is perhaps less elegant than describing them in terms of MOV32r0 and subreg operations, but it allows the current register to rematerialize them. llvm-svn: 93158
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