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* Define instructions for cmovo and cmovno.Dan Gohman2009-01-071-0/+20
| | | | llvm-svn: 61836
* Fix some JIT encodings.Chris Lattner2008-12-251-4/+4
| | | | llvm-svn: 61425
* BT memory operands load from their address operand.Chris Lattner2008-12-251-1/+1
| | | | llvm-svn: 61424
* Add instruction patterns and encodings for the x86 bt instructions.Dan Gohman2008-12-231-0/+14
| | | | llvm-svn: 61400
* Move the patterns which have i8 immediates before the patternsDan Gohman2008-12-191-99/+99
| | | | | | | | that have i32 immediates so that they get selected first. This currently only matters in the JIT, as assemblers will automatically use the smallest encoding. llvm-svn: 61250
* - Use patterns instead of creating completely new instruction matching patterns,Bill Wendling2008-12-121-151/+138
| | | | | | | | | | which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
* Redo the arithmetic with overflow architecture. I was changing the semantics ofBill Wendling2008-12-121-52/+184
| | | | | | | | | | | | ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
* Add sub/mul overflow intrinsics. This currently doesn't have aBill Wendling2008-12-091-13/+26
| | | | | | | target-independent way of determining overflow on multiplication. It's very tricky. Patch by Zoltan Varga! llvm-svn: 60800
* Fix typo, psuedo -> pseudo.Nick Lewycky2008-12-071-8/+8
| | | | llvm-svn: 60651
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS".Bill Wendling2008-12-021-9/+16
| | | | llvm-svn: 60385
* Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail.Bill Wendling2008-12-011-28/+14
| | | | llvm-svn: 60383
* - Have "ADD" instructions return an implicit EFLAGS.Bill Wendling2008-12-011-14/+28
| | | | | | - Add support for seto, setno, setc, and setnc instructions. llvm-svn: 60382
* Don't set neverHasSideEffects on x86's divide instructions, sinceDan Gohman2008-11-181-2/+0
| | | | | | | they trap on divide-by-zero, and this side effect is otherwise unmodeled. llvm-svn: 59551
* Fix PEXTRQ encodingNate Begeman2008-10-291-1/+1
| | | | llvm-svn: 58403
* Fun x86 encoding tricks: when adding an immediate value of 128,Dan Gohman2008-10-171-8/+15
| | | | | | | | | | | | | use a SUB instruction instead of an ADD, because -128 can be encoded in an 8-bit signed immediate field, while +128 can't be. This avoids the need for a 32-bit immediate field in this case. A similar optimization applies to 64-bit adds with 0x80000000, with the 32-bit signed immediate field. To support this, teach tablegen how to handle 64-bit constants. llvm-svn: 57663
* Define patterns for shld and shrd that match immediateDan Gohman2008-10-171-0/+32
| | | | | | | | | | | | | | | | | | shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
* Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's asChris Lattner2008-10-111-2/+2
| | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. llvm-svn: 57385
* Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms.Dan Gohman2008-10-011-1/+20
| | | | | | | | | | | This allows the 64-bit forms to use+def RSP instead of ESP. This doesn't fix any real bugs today, but it is more precise and it makes the debug dumps on x86-64 look more consistent. Also, add some comments describing the CALL instructions' physreg operand uses and defs. llvm-svn: 56925
* Mark CALL instructions as having a Use of ESP/RSP.Dan Gohman2008-10-011-1/+2
| | | | llvm-svn: 56911
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-161-1/+1
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-161-1/+1
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-4/+4
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Reapply 55899: First draft of EH support on x86/64-linuxAnton Korobeynikov2008-09-081-0/+11
| | | | | | | Now with fix, which prevents subtle codegen bug to trigger on darwin. No fix for bug though, it's still there. llvm-svn: 55955
* Reverting r55898 to r55909. One of these patches was causing an ICE during ↵Bill Wendling2008-09-081-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the full bootstrap on Darwin: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include -DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o libgcc/x86_64/_negdi2_s.o Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311. /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include -DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o libgcc/x86_64/_lshrdi3_s.o ../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. {standard input}:unknown:Undefined local symbol LBB21_11 {standard input}:unknown:Undefined local symbol LBB21_12 {standard input}:unknown:Undefined local symbol LBB21_13 {standard input}:unknown:Undefined local symbol LBB21_8 llvm-svn: 55928
* First draft of EH support on x86/64-linuxAnton Korobeynikov2008-09-081-0/+11
| | | | llvm-svn: 55899
* For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But ↵Evan Cheng2008-08-301-1/+1
| | | | | | various passes cannot handle remating these. llvm-svn: 55562
* Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 ↵Evan Cheng2008-08-301-0/+16
| | | | | | shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
* Split the ATOMIC NodeType's to include the size, e.g.Dale Johannesen2008-08-281-8/+8
| | | | | | | | | | | | | | | | ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD. Increased the Hardcoded Constant OpActionsCapacity to match. Large but boring; no functional change. This is to support partial-word atomics on ppc; i8 is not a valid type there, so by the time we get to lowering, the ATOMIC_LOAD nodes looks the same whether the type was i8 or i32. The information can be added to the AtomicSDNode, but that is the largest SDNode; I don't fully understand the SDNode allocation, but it is sensitive to the largest node size, so increasing that must be bad. This is the alternative. llvm-svn: 55457
* Reinstate the x86-64 portion of r55190. When doing extloads intoDan Gohman2008-08-271-9/+8
| | | | | | | | 64-bit registers from 16-bit and smaller memory locations, prefer instructions that define the entire 64-bit register, to avoid partial-register updates. llvm-svn: 55422
* Fix asm printing of MOVSDto64mr and MOV64toSDrm.Evan Cheng2008-08-251-2/+2
| | | | llvm-svn: 55300
* Reverting r55190, r55191, and r55192. They broke the build with this error ↵Bill Wendling2008-08-221-3/+9
| | | | | | | | | | | | | | | message: {standard input}:17:bad register name `%sil' make[4]: *** [libgcc/./_addvsi3.o] Error 1 make[4]: *** Waiting for unfinished jobs.... {standard input}:23:bad register name `%dil' {standard input}:28:bad register name `%dil' make[4]: *** [libgcc/./_addvdi3.o] Error 1 {standard input}:18:bad register name `%sil' make[4]: *** [libgcc/./_subvsi3.o] Error 1 llvm-svn: 55200
* Anyext tweaks for x86. When extloading a value to i32 or i64, chooseDan Gohman2008-08-221-9/+3
| | | | | | | | instructions that define the full 32 or 64-bit value. When anyexting from i8 to i16 or i32, it's not necessary to zero out the high portion of the register. llvm-svn: 55190
* Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATEDan Gohman2008-08-201-16/+60
| | | | | | | | | | | | | out of X86ISelDAGToDAG.cpp C++ code and into tablegen code. Among other things, using tablegen for these things makes them friendlier to FastISel. Tablegen can handle the case of i8 subregs on x86-32, but currently the C++ code for that case uses MVT::Flag in a tricky way, and it happens to schedule better in some cases. So for now, leave the C++ code in place to handle the i8 case on x86-32. llvm-svn: 55078
* Add remaining 64-bit atomic patterns for x86-64.Dale Johannesen2008-08-201-0/+28
| | | | llvm-svn: 55029
* Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.Bill Wendling2008-08-201-7/+0
| | | | | | Just expand it like the other X-bit sub_and_fetches. llvm-svn: 55023
* Add support for the __sync_sub_and_fetch atomics and friends for X86. The codeBill Wendling2008-08-191-3/+10
| | | | | | was already present, but not hooked up to anything. llvm-svn: 55018
* Add support for 8 and 16 bit forms of __syncDale Johannesen2008-08-191-2/+2
| | | | | | | | | | builtins on X86. Change "lock" instructions to be on a separate line. This is needed to work around a bug in the Darwin assembler. llvm-svn: 54999
* Re-enable elimination of unnecessary SUBREG_TO_REG instructions inDan Gohman2008-08-071-8/+15
| | | | | | | | | | | LowerSubregs, and fix an x86-64 isel bug that this exposed. SUBREG_TO_REG for x86-64 implicit zero extension is only safe for isel to generate when the source is known to always have zeros in the high 32 bits. The EXTRACT_SUBREG instruction does not clear the high 32 bits. llvm-svn: 54444
* Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,Dan Gohman2008-08-061-6/+0
| | | | | | | this time using MOV32to32_ and MOV16to16_. Thanks to Evan for suggesting this. llvm-svn: 54418
* xchg does not modify FLAGS.Dan Gohman2008-08-061-1/+2
| | | | llvm-svn: 54411
* Reapply r54147 with a constraint to only use the 8-bitDan Gohman2008-07-301-15/+39
| | | | | | | | | | | subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
* Revert 54147.Dan Gohman2008-07-291-6/+0
| | | | llvm-svn: 54148
* Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,Dan Gohman2008-07-281-0/+6
| | | | | | | | which is represented in codegen as an 'and' operation. This matches them with movz instructions, instead of leaving them to be matched by and instructions with an immediate field. llvm-svn: 54147
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-1/+1
| | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub llvm-svn: 52706
* Enable two-address remat by default.Evan Cheng2008-06-251-1/+1
| | | | llvm-svn: 52701
* Add the "AsCheapAsAMove" flag to some 64-bit xor instructions.Bill Wendling2008-05-301-2/+3
| | | | llvm-svn: 51761
* Add patterns for CALL32m and CALL64m. They aren't matched in mostDan Gohman2008-05-291-1/+1
| | | | | | | | | | | | cases due to an isel deficiency already noted in lib/Target/X86/README.txt, but they can be matched in this fold-call.ll testcase, for example. This is interesting mainly because it exposes a tricky tblgen bug; tblgen was incorrectly computing the starting index for variable_ops in the case of a complex pattern. llvm-svn: 51706
* Fix 80col violationAnton Korobeynikov2008-05-051-1/+1
| | | | llvm-svn: 50654
* Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look ↵Anton Korobeynikov2008-05-041-0/+7
| | | | | | | | for tlsaddr pattern), but should work. Work is in progress, more models will follow llvm-svn: 50630
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