| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 26246
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llvm-svn: 26069
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llvm-svn: 25776
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llvm-svn: 25679
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llvm-svn: 25595
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llvm-svn: 25515
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Some assemblers can't recognize the aliases.
llvm-svn: 25494
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llvm-svn: 25333
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llvm-svn: 25293
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llvm-svn: 25278
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llvm-svn: 25257
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llvm-svn: 25226
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* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
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llvm-svn: 25192
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llvm-svn: 25129
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that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
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12/14/2005 hbd failure.
llvm-svn: 24717
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llvm-svn: 24585
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This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on. Given a clean nightly tester run, we should be able to turn it
on by default!
llvm-svn: 24578
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llvm-svn: 24430
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contributed by Evan Cheng.
llvm-svn: 24358
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Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
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llvm-svn: 23754
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fixing a bunch of nasty hackery
llvm-svn: 23735
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llvm-svn: 23594
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Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
llvm-svn: 23505
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llvm-svn: 23347
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llvm-svn: 23332
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llvm-svn: 23202
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llvm-svn: 23119
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llvm-svn: 23082
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putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
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llvm-svn: 23031
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llvm-svn: 22888
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only take one operand. The other comes implicitly in through CL.
llvm-svn: 22887
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llvm-svn: 22807
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fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
llvm-svn: 22805
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block. nur.
llvm-svn: 22788
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now generate the relatively good code sequences:
unsigned short foo(float a) { return a; }
_foo:
movss 4(%esp), %xmm0
cvttss2si %xmm0, %eax
movzwl %ax, %eax
ret
and
unsigned bar(float a) { return a; }
_bar:
movss .CPI_bar_0, %xmm0
movss 4(%esp), %xmm1
movapd %xmm1, %xmm2
subss %xmm0, %xmm2
cvttss2si %xmm2, %eax
xorl $-2147483648, %eax
cvttss2si %xmm1, %ecx
ucomiss %xmm0, %xmm1
cmovb %ecx, %eax
ret
llvm-svn: 22786
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llvm-svn: 22729
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llvm-svn: 22687
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Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted
llvm-svn: 22637
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Patch contributed by Jim Laskey!
llvm-svn: 22594
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llvm-svn: 22565
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llvm-svn: 22561
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1 byte loads and other operations. This is bad for store-forwarding on
common CPUs. We now do this:
fnstcw WORD PTR [%ESP]
mov %AX, WORD PTR [%ESP]
instead of:
fnstcw WORD PTR [%ESP]
mov %AL, BYTE PTR [%ESP + 1]
llvm-svn: 22559
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FP-to-int-in-memory: this exposes the load from the stored slot to the
selection dag, allowing it to be folded into other operaions.
llvm-svn: 22556
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that the X86 does not support to the legalizer. This allows it to be better
optimized, etc, and will help with SSE support.
llvm-svn: 22551
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llvm-svn: 22550
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long %test4(double %X) {
%tmp.1 = cast double %X to long ; <long> [#uses=1]
ret long %tmp.1
}
to this:
_test4:
sub %ESP, 12
fld QWORD PTR [%ESP + 16]
fistp QWORD PTR [%ESP]
mov %EDX, DWORD PTR [%ESP + 4]
mov %EAX, DWORD PTR [%ESP]
add %ESP, 12
ret
instead of this:
_test4:
sub %ESP, 28
fld QWORD PTR [%ESP + 32]
fstp QWORD PTR [%ESP]
call ___fixdfdi
add %ESP, 28
ret
llvm-svn: 22549
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