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path: root/llvm/lib/Target/X86/X86ISelPattern.cpp
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* Fix some mysteriously missing {}'s which cause the miscompilation ofChris Lattner2005-04-131-2/+2
| | | | | | Olden/mst, Ptrdist/bc, Obsequi, etc. llvm-svn: 21274
* Z_E_I is goneChris Lattner2005-04-131-2/+0
| | | | llvm-svn: 21267
* Use live out sets for return values instead of imp_defs, which is cleaner ↵Chris Lattner2005-04-091-6/+20
| | | | | | and faster. llvm-svn: 21181
* This target does not support/want ISD::BRCONDTWOWAYChris Lattner2005-04-091-0/+1
| | | | llvm-svn: 21164
* X86 zero extends setcc resultsChris Lattner2005-04-071-0/+1
| | | | llvm-svn: 21146
* Add (untested) support for MULHS and MULHU.Chris Lattner2005-04-061-0/+51
| | | | llvm-svn: 21107
* add support for FABS and FNEGChris Lattner2005-04-021-4/+10
| | | | llvm-svn: 21015
* This target doesn't support fabs/fneg yet.Chris Lattner2005-04-021-0/+4
| | | | llvm-svn: 21010
* Add support for 64-bit shifts.Chris Lattner2005-04-021-16/+84
| | | | llvm-svn: 21005
* Add support for ISD::UNDEF to the X86 beChris Lattner2005-04-011-0/+8
| | | | llvm-svn: 20990
* don't depend on the cfg being set up yetChris Lattner2005-03-301-1/+1
| | | | llvm-svn: 20936
* Change interface to LowerCallTo to take a boolean isVarArg argument.Nate Begeman2005-03-261-4/+4
| | | | llvm-svn: 20842
* Remove comments that are now meaningless from the pattern ISels, at Chris'sNate Begeman2005-03-241-2/+1
| | | | | | request. llvm-svn: 20804
* Don't emit two comparisons when comparing a FP value against zero!Chris Lattner2005-03-171-0/+1
| | | | llvm-svn: 20651
* This mega patch converts us from using Function::a{iterator|begin|end} toChris Lattner2005-03-151-1/+1
| | | | | | | | using Function::arg_{iterator|begin|end}. Likewise Module::g* -> Module::global_*. This patch is contributed by Gabor Greif, thanks! llvm-svn: 20597
* Silence some uninit variable warnings.Chris Lattner2005-02-231-0/+2
| | | | llvm-svn: 20284
* We can fold promoted and non-promoted loads into divs also!Chris Lattner2005-01-251-0/+28
| | | | llvm-svn: 19835
* Fold promoted loads into binary ops for FP, allowing us to generate m32 formsChris Lattner2005-01-251-20/+31
| | | | | | of FP ops. llvm-svn: 19834
* Silence a warning.Chris Lattner2005-01-231-1/+1
| | | | llvm-svn: 19798
* Speed up folding operations into loads.Chris Lattner2005-01-211-1/+2
| | | | llvm-svn: 19733
* The ever-important vanity pass name :)Chris Lattner2005-01-211-0/+4
| | | | llvm-svn: 19731
* Fix a FIXME: realize that argument stores are all independent (don't alias)Chris Lattner2005-01-211-6/+7
| | | | llvm-svn: 19728
* Implement ADD_PARTS/SUB_PARTS so that 64-bit integer add/sub work. ThisChris Lattner2005-01-201-6/+32
| | | | | | fixes most of the remaining llc-beta failures. llvm-svn: 19716
* Fix a crash compiling 134.perl.Chris Lattner2005-01-201-21/+41
| | | | llvm-svn: 19711
* Fix a problem where were were literally selecting for INCREASED registerChris Lattner2005-01-191-8/+8
| | | | | | | | pressure, not decreases register pressure. Fix problem where we accidentally swapped the operands of SHLD, which caused fourinarow to fail. This fixes fourinarow. llvm-svn: 19697
* Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (whichChris Lattner2005-01-191-38/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | typically cost 1 cycle) instead of shld/shrd instruction (which are typically 6 or more cycles). This also saves code space. For example, instead of emitting: rotr: mov %EAX, DWORD PTR [%ESP + 4] mov %CL, BYTE PTR [%ESP + 8] shrd %EAX, %EAX, %CL ret rotli: mov %EAX, DWORD PTR [%ESP + 4] shrd %EAX, %EAX, 27 ret Emit: rotr32: mov %CL, BYTE PTR [%ESP + 8] mov %EAX, DWORD PTR [%ESP + 4] ror %EAX, %CL ret rotli32: mov %EAX, DWORD PTR [%ESP + 4] ror %EAX, 27 ret We also emit byte rotate instructions which do not have a sh[lr]d counterpart at all. llvm-svn: 19692
* Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5Chris Lattner2005-01-191-16/+20
| | | | llvm-svn: 19689
* Codegen long >> 2 to this:Chris Lattner2005-01-191-1/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shrd %EAX, %EDX, 2 sar %EDX, 2 ret instead of this: test1: mov %ECX, DWORD PTR [%ESP + 4] shr %ECX, 2 mov %EDX, DWORD PTR [%ESP + 8] mov %EAX, %EDX shl %EAX, 30 or %EAX, %ECX sar %EDX, 2 ret and long << 2 to this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] *** mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, %EAX shr %ECX, 30 mov %EDX, DWORD PTR [%ESP + 8] shl %EDX, 2 or %EDX, %ECX shl %EAX, 2 ret The extra copy (marked ***) can be eliminated when I teach the code generator that shrd32rri8 is really commutative. llvm-svn: 19681
* X86 shifts mask the amount.Chris Lattner2005-01-191-0/+1
| | | | llvm-svn: 19678
* Code to handle FP_EXTEND is dead now. X86 doesn't support any data types toChris Lattner2005-01-181-4/+1
| | | | | | FP_EXTEND from! llvm-svn: 19674
* Remove more dead code.Chris Lattner2005-01-181-17/+0
| | | | llvm-svn: 19673
* The selection dag code handles the promotions from F32 to F64 for us, so weChris Lattner2005-01-181-12/+0
| | | | | | don't need to even think about F32 in the X86 code anymore. llvm-svn: 19672
* Fix 124.m88ksim.Chris Lattner2005-01-181-0/+3
| | | | llvm-svn: 19667
* Do not emit loads multiple times, potentially in the wrong places.Chris Lattner2005-01-181-2/+2
| | | | llvm-svn: 19661
* Eliminate bad assertions.Chris Lattner2005-01-181-0/+2
| | | | llvm-svn: 19659
* * Eliminate the TokenSet and just use the ExprMap for both tokens and values.Chris Lattner2005-01-181-14/+13
| | | | | | | | * Insert some really pedantic assertions that will notice when we emit the same loads more than one time, exposing bugs. This turns a miscompilation in bzip2 into a compile-fail. yaay. llvm-svn: 19658
* Rely on the code in MatchAddress to do this work. Otherwise we fail toChris Lattner2005-01-181-11/+13
| | | | | | | match (X+Y)+(Z << 1), because we match the X+Y first, consuming the index register, then there is no place to put the Z. llvm-svn: 19652
* Fix a problem where probing for addressing modes caused expressions to beChris Lattner2005-01-181-33/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | emitted too early. In particular, this fixes Regression/CodeGen/X86/regpressure.ll:regpressure3. This also improves the 2nd basic block in 164.gzip:flush_block, which went from .LBBflush_block_1: # loopentry.1.i movzx %EAX, WORD PTR [dyn_ltree + 20] movzx %ECX, WORD PTR [dyn_ltree + 16] mov DWORD PTR [%ESP + 32], %ECX movzx %ECX, WORD PTR [dyn_ltree + 12] movzx %EDX, WORD PTR [dyn_ltree + 8] movzx %EBX, WORD PTR [dyn_ltree + 4] mov DWORD PTR [%ESP + 36], %EBX movzx %EBX, WORD PTR [dyn_ltree] add DWORD PTR [%ESP + 36], %EBX add %EDX, DWORD PTR [%ESP + 36] add %ECX, %EDX add DWORD PTR [%ESP + 32], %ECX add %EAX, DWORD PTR [%ESP + 32] movzx %ECX, WORD PTR [dyn_ltree + 24] add %EAX, %ECX mov %ECX, 0 mov %EDX, %ECX to .LBBflush_block_1: # loopentry.1.i movzx %EAX, WORD PTR [dyn_ltree] movzx %ECX, WORD PTR [dyn_ltree + 4] add %ECX, %EAX movzx %EAX, WORD PTR [dyn_ltree + 8] add %EAX, %ECX movzx %ECX, WORD PTR [dyn_ltree + 12] add %ECX, %EAX movzx %EAX, WORD PTR [dyn_ltree + 16] add %EAX, %ECX movzx %ECX, WORD PTR [dyn_ltree + 20] add %ECX, %EAX movzx %EAX, WORD PTR [dyn_ltree + 24] add %ECX, %EAX mov %EAX, 0 mov %EDX, %EAX ... which results in less spilling in the function. This change alone speeds up 164.gzip from 37.23s to 36.24s on apoc. The default isel takes 37.31s. llvm-svn: 19650
* Don't bother using max here.Chris Lattner2005-01-171-1/+1
| | | | llvm-svn: 19647
* Do not give token factor nodes outrageous weightsChris Lattner2005-01-171-2/+5
| | | | llvm-svn: 19645
* Two changes:Chris Lattner2005-01-171-5/+74
| | | | | | | 1. Fold [mem] += (1|-1) into inc [mem]/dec [mem] to save some icache space. 2. Do not let token factor nodes prevent forming '[mem] op= val' folds. llvm-svn: 19643
* Refactor load/op/store folding into it's own method, no functionality changes.Chris Lattner2005-01-171-125/+141
| | | | llvm-svn: 19641
* Fix a major regression last night that prevented us from producing [mem] op= regChris Lattner2005-01-171-109/+111
| | | | | | | | operations. The body of the if is less indented but unmodified in this patch. llvm-svn: 19638
* Codegen this:Chris Lattner2005-01-171-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | int %foo(int %X) { %T = add int %X, 13 %S = mul int %T, 3 ret int %S } as this: mov %ECX, DWORD PTR [%ESP + 4] lea %EAX, DWORD PTR [%ECX + 2*%ECX + 39] ret instead of this: mov %ECX, DWORD PTR [%ESP + 4] mov %EAX, %ECX add %EAX, 13 imul %EAX, %EAX, 3 ret llvm-svn: 19633
* Fix test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll and 132.ijpeg.Chris Lattner2005-01-171-17/+62
| | | | | | | | Do not fold a load into an operation if it will induce a cycle in the DAG. Repeat after me: dAg. llvm-svn: 19631
* Do not fold a load into a comparison that is used by more than one place.Chris Lattner2005-01-171-8/+8
| | | | | | | The comparison will probably be folded, so this is not ok to do. This fixed 197.parser. llvm-svn: 19624
* Do not codegen 'xor bool, true' as 'not reg'. not reg inverts the upper bitsChris Lattner2005-01-171-4/+7
| | | | | | of the bytereg. This fixes yacr2, 300.twolf and probably others. llvm-svn: 19622
* Set up the shift and setcc types.Chris Lattner2005-01-171-1/+32
| | | | | | | If we emit a load because we followed a token chain to get to it, try to fold it into its single user if possible. llvm-svn: 19620
* * Adjust to changes in TargetLowering interfaces.Chris Lattner2005-01-161-43/+52
| | | | | | | | | | | | * Remove custom promotion for bool and byte select ops. Legalize now promotes them for us. * Allow folding ConstantPoolIndexes into EXTLOAD's, useful for float immediates. * Declare which operations are not supported better. * Add some hacky code for TRUNCSTORE to pretend that we have truncstore for i16 types. This is useful for testing promotion code because I can just remove 16-bit registers all together and verify that programs work. llvm-svn: 19614
* Add support for truncstore and *extload.Chris Lattner2005-01-151-2/+142
| | | | llvm-svn: 19566
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