| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AVX] Support VSINSERTF128 with more patterns and appropriate | David Greene | 2011-02-04 | 1 | -0/+10 |
| * | [AVX] VEXTRACTF128 support. This commit includes patterns for | David Greene | 2011-02-03 | 1 | -0/+10 |
| * | [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a | David Greene | 2011-01-26 | 1 | -0/+1 |
| * | [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default | David Greene | 2011-01-26 | 1 | -0/+1 |
| * | Implement feedback from Bruno on making pblendvb an x86-specific ISD node in ... | Nate Begeman | 2010-12-20 | 1 | -0/+3 |
| * | Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which | Chris Lattner | 2010-12-20 | 1 | -3/+3 |
| * | improve the setcc -> setcc_carry optimization to happen more | Chris Lattner | 2010-12-19 | 1 | -1/+1 |
| * | Add support for matching psign & plendvb to the x86 target | Nate Begeman | 2010-12-17 | 1 | -1/+7 |
| * | it turns out that when ".with.overflow" intrinsics were added to the X86 | Chris Lattner | 2010-12-05 | 1 | -2/+4 |
| * | Enable sibling call optimization of libcalls which are expanded during | Evan Cheng | 2010-11-30 | 1 | -0/+2 |
| * | Fix some cleanups from my last patch. | Eric Christopher | 2010-11-30 | 1 | -2/+2 |
| * | Rewrite mwait and monitor support and custom lower arguments. | Eric Christopher | 2010-11-30 | 1 | -0/+7 |
| * | Lower TLS_addr32 and TLS_addr64. | Rafael Espindola | 2010-11-27 | 1 | -0/+3 |
| * | Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. | Wesley Peck | 2010-11-23 | 1 | -1/+1 |
| * | On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics, | Duncan Sands | 2010-11-20 | 1 | -6/+6 |
| * | move the pic base symbol stuff up to MachineFunction | Chris Lattner | 2010-11-14 | 1 | -3/+0 |
| * | simplify getPICBaseSymbol a bit. | Chris Lattner | 2010-11-14 | 1 | -1/+1 |
| * | Factorize the duplicated logic for choosing the right argument | Duncan Sands | 2010-10-31 | 1 | -1/+0 |
| * | Inline asm multiple alternative constraints development phase 2 - improved ba... | John Thompson | 2010-10-29 | 1 | -3/+2 |
| * | X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. | Michael J. Spencer | 2010-10-21 | 1 | -3/+3 |
| * | Fix Whitespace. | Michael J. Spencer | 2010-10-20 | 1 | -36/+36 |
| * | Initial va_arg support for x86-64. Patch by David Meyer! | Dan Gohman | 2010-10-12 | 1 | -1/+10 |
| * | Massive rewrite of MMX: | Dale Johannesen | 2010-09-30 | 1 | -3/+7 |
| * | reimplement elf TLS support in terms of addressing modes, eliminating Segment... | Chris Lattner | 2010-09-22 | 1 | -3/+0 |
| * | convert the last 4 X86ISD nodes that should have memoperands to have them. | Chris Lattner | 2010-09-22 | 1 | -21/+21 |
| * | give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only | Chris Lattner | 2010-09-22 | 1 | -3/+2 |
| * | give FP_TO_INT16_IN_MEM and friends a memoperand. They are only | Chris Lattner | 2010-09-22 | 1 | -11/+12 |
| * | give VZEXT_LOAD a memory operand, it now works with segment registers. | Chris Lattner | 2010-09-22 | 1 | -4/+4 |
| * | give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256... | Chris Lattner | 2010-09-21 | 1 | -5/+5 |
| * | Reimplement r114460 in target-independent DAGCombine rather than target-depen... | Owen Anderson | 2010-09-21 | 1 | -0/+5 |
| * | Added skeleton for inline asm multiple alternative constraint support. | John Thompson | 2010-09-13 | 1 | -0/+6 |
| * | Use movlps, movlpd, movss and movsd specific nodes instead of pattern matchin... | Bruno Cardoso Lopes | 2010-09-01 | 1 | -0/+2 |
| * | Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless... | Bruno Cardoso Lopes | 2010-08-31 | 1 | -5/+1 |
| * | Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly | Bruno Cardoso Lopes | 2010-08-21 | 1 | -0/+3 |
| * | This is the first step towards refactoring the x86 vector shuffle code. The | Bruno Cardoso Lopes | 2010-08-20 | 1 | -0/+37 |
| * | Add AVX matching patterns to Packed Bit Test intrinsics. | Bruno Cardoso Lopes | 2010-08-10 | 1 | -0/+3 |
| * | ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller ... | Nate Begeman | 2010-07-27 | 1 | -0/+1 |
| * | On x86, f32 / f64 nodes share the same registers as 128-bit vector values. | Evan Cheng | 2010-07-26 | 1 | -0/+4 |
| * | Add an ILP scheduler. This is a register pressure aware scheduler that's | Evan Cheng | 2010-07-24 | 1 | -0/+3 |
| * | Custom lower the memory barrier instructions and add support | Eric Christopher | 2010-07-22 | 1 | -1/+8 |
| * | Pulling out previous patch, must've run the tests in | Eric Christopher | 2010-07-21 | 1 | -5/+1 |
| * | Lower MEMBARRIER on x86 and support processors without SSE2. | Eric Christopher | 2010-07-21 | 1 | -1/+5 |
| * | Use TargetOpcode::COPY instead of X86-native register copy instructions when | Jakob Stoklund Olesen | 2010-07-14 | 1 | -1/+0 |
| * | Reapply bottom-up fast-isel, with several fixes for x86-32: | Dan Gohman | 2010-07-10 | 1 | -2/+1 |
| * | --- Reverse-merging r107947 into '.': | Bob Wilson | 2010-07-09 | 1 | -1/+2 |
| * | Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting | Dan Gohman | 2010-07-09 | 1 | -2/+1 |
| * | Revert 107840 107839 107813 107804 107800 107797 107791. | Dan Gohman | 2010-07-08 | 1 | -1/+2 |
| * | Add X86FastISel support for return statements. This entails refactoring | Dan Gohman | 2010-07-07 | 1 | -2/+1 |
| * | Simplify FastISel's constructor by giving it a FunctionLoweringInfo | Dan Gohman | 2010-07-07 | 1 | -19/+2 |
| * | Split the SDValue out of OutputArg so that SelectionDAG-independent | Dan Gohman | 2010-07-07 | 1 | -0/+3 |
