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* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-2/+2
| | | | llvm-svn: 238634
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-3/+3
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-151-2/+2
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* MC: Update MCFixup naming. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/MCFixup::Create/MCFixup::create/ llvm-svn: 237468
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-1/+1
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-3/+3
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-3/+3
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-1/+1
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-3/+3
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-3/+3
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-101-2/+0
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-3/+3
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-3/+3
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for ↵Aaron Ballman2015-02-151-2/+2
| | | | | | requiring the macro. NFC; LLVM edition. llvm-svn: 229340
* [X86] Add the remaining 11 possible exact ModRM formats. This makes their ↵Craig Topper2015-02-151-73/+21
| | | | | | encodings linear which can then be used to simplify some other code. llvm-svn: 229279
* [X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper2014-12-241-10/+4
| | | | | | | | AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
* x86: Emit LOCK prefix after DATA16JF Bastien2014-12-151-4/+6
| | | | | | | | | | | | | | Summary: x86 allows either ordering for the LOCK and DATA16 prefixes, but using GCC+GAS leads to different code generation than using LLVM. This change matches the order that GAS emits the x86 prefixes when a semicolon isn't used in inline assembly (see tc-i386.c comment before define LOCK_PREFIX), and helps simplify tooling that operates on the instruction's byte sequence (such as NaCl's validator). This change shouldn't have any performance impact. Test Plan: ninja check Reviewers: craig.topper, jvoung Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6630 llvm-svn: 224283
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-2/+2
| | | | llvm-svn: 223339
* Use uint64_t as the type for the X86 TSFlag format enum. Allows removal of ↵Craig Topper2014-11-111-31/+26
| | | | | | the VEXShift hack that was used to access the higher bits of TSFlags. llvm-svn: 221673
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-311-14/+17
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* [X86] AVX512: Use the TD version of CD8_Scale in the assemblerAdam Nemet2014-07-171-40/+7
| | | | | | | | | | | Passes the computed scaling factor in TSFlags rather than the old attributes. Also removes the C++ version of computing the scaling factor (MemObjSize) along with the asserts added by the previous patch. No functional change. llvm-svn: 213279
* [X86] AVX512: Move compressed displacement logic to TDAdam Nemet2014-07-171-0/+4
| | | | | | | | | | | | | | | This does not actually move the logic yet but reimplements it in the Tablegen language. Then asserts that the new implementation results in the same value. The next patch will remove the assert and the temporary use of the TSFlags and remove the C++ implementation. The formula requires a limited form of the logical left and right operators. I implemented these with the bit-extract/insert operator (i.e. blah{bits}). No functional change. llvm-svn: 213278
* [X86] AVX512: Improve readability of isCDisp8Adam Nemet2014-07-111-3/+12
| | | | | | | | No functional change. As I was trying to understand this function, I found that variables were reused with confusing names and the broadcast case was a bit too implicit. Hopefully, this is an improvement. llvm-svn: 212795
* [X86] AVX512: Simplify logic in isCDisp8Adam Nemet2014-07-111-6/+6
| | | | | | | | | | | | It was computing the VL/n case as: MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize ElemByteSize not only falls out but VectorByteSize/Divider now actually matches the definition of VL/n. Also some formatting fixes. llvm-svn: 212794
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-121-0/+4
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* Handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode.Rafael Espindola2014-04-211-1/+7
| | | | | | | | | With this MC is able to handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode, which is needed for medium and large code models. This fixes pr19470. llvm-svn: 206793
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-1/+1
| | | | | | class. llvm-svn: 203418
* AVX-512: fixed comressed displacement - by Robert KhazanovElena Demikhovsky2014-03-061-1/+1
| | | | llvm-svn: 203096
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-7/+34
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-17/+11
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-4/+12
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-11/+4
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-4/+11
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* AVX-512: fixed a bug in EVEX encoding (the bug appeared after r200624)Elena Demikhovsky2014-02-051-2/+4
| | | | llvm-svn: 200837
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-4/+5
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-33/+37
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-311-90/+33
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-311-2/+1
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* Move address override handling in X86MCCodeEmitter to a place where it works ↵Craig Topper2014-01-311-46/+43
| | | | | | for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode. llvm-svn: 200516
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-301-10/+7
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
* Delete MCSubtargetInfo data members from target MCCodeEmitter classesDavid Woodhouse2014-01-281-38/+38
| | | | | | | | The subtarget info is explicitly passed to the EncodeInstruction method and we should use that subtarget info to influence any encoding decisions. llvm-svn: 200350
* Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()David Woodhouse2014-01-281-2/+4
| | | | llvm-svn: 200348
* [x86] Silence unused diReg variable warning in non-asserting buildsDavid Woodhouse2014-01-221-4/+3
| | | | llvm-svn: 199812
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+18
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+10
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+13
| | | | llvm-svn: 199803
* Replace duplicated code with a existing helper function.Craig Topper2014-01-171-16/+1
| | | | llvm-svn: 199468
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-13/+20
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
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