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* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-061-0/+23
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-232-2/+2
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-192-2/+2
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-092-8/+10
| | | | llvm-svn: 239370
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-302-2/+2
| | | | llvm-svn: 238634
* Print "lock \t foo" instead of "lock \n foo".Rafael Espindola2015-05-261-1/+1
| | | | | | | | | | | This gets gas and llc -filetype=obj to agree on the order of prefixes. For llvm-mc we need to fix the asm parser to know that it makes a difference on which line the "lock" is in. Part of pr23594. llvm-svn: 238232
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-1/+1
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* Reformat.NAKAMURA Takumi2015-05-251-65/+64
| | | | llvm-svn: 238126
* Prune CRLFs.NAKAMURA Takumi2015-05-251-982/+982
| | | | llvm-svn: 238125
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-1/+1
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-1/+1
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Remove unused MCSubtargetInfo argument from the X86 MCInstPrinter ctors.Eric Christopher2015-03-301-1/+1
| | | | llvm-svn: 233614
* [X86] Read the feature bits from the subtarget that is passed to printInstAkira Hatanaka2015-03-282-5/+2
| | | | | | instead of from MCInstPrinter::AvailableFeatures. llvm-svn: 233485
* Partially revert the changes I made in r233473 to keep the code concise.Akira Hatanaka2015-03-281-137/+47
| | | | llvm-svn: 233474
* clang-format X86ATTInstPrinter.{h,cpp} before I make changes to these files.Akira Hatanaka2015-03-282-76/+156
| | | | llvm-svn: 233473
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-274-4/+7
| | | | | | | | | | | | | | | | | | | | per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-1/+1
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-1/+1
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-1/+1
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-1/+1
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [X86] Add support for parsing and printing the mnemonic aliases for the XOP ↵Craig Topper2015-02-134-2/+36
| | | | | | VPCOM instructions. llvm-svn: 229078
* [X86][SSE] Shuffle mask decode support for zero extend, scalar float/double ↵Simon Pilgrim2015-01-311-0/+172
| | | | | | | | | | | | moves and integer load instructions This patch adds shuffle mask decodes for integer zero extends (pmovzx** and movq xmm,xmm) and scalar float/double loads/moves (movss/movsd). Also adds shuffle mask decodes for integer loads (movd/movq). Differential Revision: http://reviews.llvm.org/D7228 llvm-svn: 227688
* Line endings fix. NFC.Simon Pilgrim2015-01-281-786/+786
| | | | llvm-svn: 227374
* [X86] Merge printSSECC and printAVXCC. They only differed by an assertion.Craig Topper2015-01-284-34/+8
| | | | llvm-svn: 227301
* [x86] Change u8imm operands to always print as unsigned. This makes shuffle ↵Craig Topper2015-01-234-0/+14
| | | | | | masks and the like make way more sense. llvm-svn: 226902
* [X86][SSE] movddup shuffle mask decodesSimon Pilgrim2015-01-211-6/+24
| | | | | | Patch to provide shuffle decodes and asm comments for the SSE3/AVX1 movddup double duplication instructions. llvm-svn: 226705
* [AVX512] Add pretty-printing of shuffle mask for unpacksAdam Nemet2015-01-131-0/+64
| | | | llvm-svn: 225837
* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the ↵Craig Topper2015-01-082-0/+8
| | | | | | LEA variants in Intel syntax. The memory operand is inherently unsized. llvm-svn: 225432
* [x86] Assert on invalid immediates in the instruction printer for ↵Craig Topper2014-12-272-4/+8
| | | | | | cmp.ps/pd/ss/sd instead of truncating the immediate. The assembly parser and instruction selection shouldn't generate invalid immediates. llvm-svn: 224886
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-262-55/+27
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* [X86] Also pretty-print shuffle mask for INSERTPS rm variants.Ahmed Bougacha2014-12-151-3/+7
| | | | llvm-svn: 224260
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-044-11/+10
| | | | llvm-svn: 223339
* [X86][SSE] pslldq/psrldq shuffle mask decodesSimon Pilgrim2014-10-141-0/+38
| | | | | | | | Patch to provide shuffle decodes and asm comments for the sse pslldq/psrldq SSE2/AVX2 byte shift instructions. Differential Revision: http://reviews.llvm.org/D5598 llvm-svn: 219738
* [x86] Implement v16i16 support with AVX2 in the new vector shuffleChandler Carruth2014-09-251-0/+11
| | | | | | | | | | | | | | | lowering. This also implements the fancy blend lowering for v16i16 using AVX2 and teaches the X86 backend to print shuffle masks for 256-bit PSHUFB and PBLENDW instructions. It also makes the mask decoding correct for PBLENDW instructions. The yaks, they are legion. Tests are updated accordingly. There are some missing tests for the VBLENDVB lowering, but I'll add those in a follow-up as this commit has accumulated enough cruft already. llvm-svn: 218430
* [x86] Teach the rest of the 'target shuffle' machinery about blends andChandler Carruth2014-09-231-0/+24
| | | | | | | | | | | add VPBLENDD to the InstPrinter's comment generation so we get nice comments everywhere. Now that we have the nice comments, I can see the bug introduced by a silly typo in the commit that enabled VPBLENDD, and have fixed it. Yay tests that are easy to inspect. llvm-svn: 218335
* [x86] Teach the vector comment parsing and printing to correctly handleChandler Carruth2014-09-231-3/+5
| | | | | | | | | | | | | | | | | undef in the shuffle mask. This shows up when we're printing comments during lowering and we still have an IR-level constant hanging around that models undef. A nice consequence of this is *much* prettier test cases where the undef lanes actually show up as undef rather than as a particular set of values. This also allows us to print shuffle comments in cases that use undef such as the recently added variable VPERMILPS lowering. Now those test cases have nice shuffle comments attached with their details. The shuffle lowering for PSHUFB has been augmented to use undef, and the shuffle combining has been augmented to comprehend it. llvm-svn: 218301
* [x86] Teach the x86 DAG combiner to form MOVSLDUP and MOVSHDUPChandler Carruth2014-09-151-0/+36
| | | | | | | | | | | | instructions when it finds an appropriate pattern. These are lovely instructions, and its a shame to not use them. =] They are fast, and can hand loads folded into their operands, etc. I've also plumbed the comment shuffle decoding through the various layers so that the test cases are printed nicely. llvm-svn: 217758
* [x32] Emit callq for CALLpcrel32Pavel Chupin2014-09-092-3/+18
| | | | | | | | | | | | | | | | | Summary: In AT&T annotation for both x86_64 and x32 calls should be printed as callq in assembly. It's only a matter of correct mnemonic, object output is ok. Test Plan: trivial test added Reviewers: nadav, dschuff, craig.topper Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D5213 llvm-svn: 217435
* [x86] Teach the asm comment printing to only print the clarification ofChandler Carruth2014-09-034-49/+64
| | | | | | | | | | an immediate operand when we don't have instruction-specific comments. This ensures that instruction-specific comments are attached to the same line as the instruction which is important for using them to write readable and maintainable tests. My next commit will just such a test. llvm-svn: 217099
* [x86] Teach the instruction printer to decode immediate operands toChandler Carruth2014-08-151-0/+64
| | | | | | | | | BLENDPS, BLENDPD, and PBLENDW instructions into pretty shuffle comments. These will be used in my next commit as part of test cases for AVX shuffles which can directly use blend in more places. llvm-svn: 215701
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-133-6/+6
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-121-0/+2
| | | | llvm-svn: 208607
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-222-2/+4
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [C++11] Mark more classes in the X86 target as 'final'.Craig Topper2014-03-312-4/+4
| | | | llvm-svn: 205166
* X86: Use enums for memory operand decoding instead of integer literals.Manuel Jacob2014-03-182-16/+16
| | | | | | | | | | | | | | | | Summary: X86BaseInfo.h defines an enum for the offset of each operand in a memory operand sequence. Some code uses it and some does not. This patch replaces (hopefully) all remaining locations where an integer literal was used instead of this enum. No functionality change intended. Reviewers: nadav CC: llvm-commits, t.p.northover Differential Revision: http://llvm-reviews.chandlerc.com/D3108 llvm-svn: 204158
* Replace ValueTypes.h with MachineValueType.h if possible.Patrik Hagglund2014-03-151-1/+1
| | | | | | | | | Utilize the previous move of MVT to a separate header for all trivial cases (that don't need any further restructuring). Reviewed By: Tim Northover llvm-svn: 204003
* Replace '#include ValueTypes.h' with forward declarations.Patrik Hagglund2014-03-121-0/+2
| | | | | | | In some cases the include is pushed "downstream" (or removed if unused). llvm-svn: 203644
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-3/+3
| | | | | | class. llvm-svn: 203418
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-2/+2
| | | | | | class. llvm-svn: 203378
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