summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-0/+3
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-1/+1
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-0/+3
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-1/+7
| | | | llvm-svn: 128826
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-2/+19
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Merge System into Support.Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120298
* add basic avx support to the disassembler, also teach it about ssmem/sdmemChris Lattner2010-09-291-0/+1
| | | | | | | | | | operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' llvm-svn: 115019
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+1
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Fixed a bug where the disassembler would allow an immediateSean Callanan2010-04-071-0/+1
| | | | | | | | | argument that had to be between 0 and 7 to have any value, firing an assert later in the AsmPrinter. Now, the disassembler rejects instructions with out-of-range values for that immediate. llvm-svn: 100694
* Fixes to the X86 disassembler:Sean Callanan2009-12-221-0/+1
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+354
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
OpenPOWER on IntegriCloud