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* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-0/+1
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-1/+49
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-1/+10
| | | | llvm-svn: 191874
* Various x86 disassembler fixes.Craig Topper2013-09-301-4/+4
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-2/+104
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-131-0/+5
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-011-1/+0
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Tidy up trailing whitespaceCraig Topper2012-07-311-12/+12
| | | | llvm-svn: 161026
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+1
| | | | llvm-svn: 153935
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-041-3/+3
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-2/+6
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-0/+3
| | | | llvm-svn: 150167
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-1/+2
| | | | llvm-svn: 143895
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-0/+3
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-1/+1
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-0/+3
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-1/+7
| | | | llvm-svn: 128826
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-2/+19
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Merge System into Support.Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120298
* add basic avx support to the disassembler, also teach it about ssmem/sdmemChris Lattner2010-09-291-0/+1
| | | | | | | | | | operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' llvm-svn: 115019
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+1
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Fixed a bug where the disassembler would allow an immediateSean Callanan2010-04-071-0/+1
| | | | | | | | | argument that had to be between 0 and 7 to have any value, firing an assert later in the AsmPrinter. Now, the disassembler rejects instructions with out-of-range values for that immediate. llvm-svn: 100694
* Fixes to the X86 disassembler:Sean Callanan2009-12-221-0/+1
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+354
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
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