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* [X86] Remove unused encoding types from disassembler. NFCCraig Topper2016-02-211-6/+0
| | | | llvm-svn: 261494
* [X86] Remove unused entries from the disassembler type enum.Craig Topper2016-02-191-4/+0
| | | | llvm-svn: 261311
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-091-0/+1
| | | | | | Added encoding tests. llvm-svn: 239403
* [X86] Remove some unused code from disassembler.Craig Topper2015-03-031-12/+0
| | | | llvm-svn: 231055
* [X86] Teach disassembler to handle illegal immediates on AVX512 integer ↵Craig Topper2015-01-281-0/+1
| | | | | | compare instructions. llvm-svn: 227302
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-211-0/+1
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-071-11/+1
| | | | llvm-svn: 225343
* [X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper2015-01-031-0/+2
| | | | | | is REX.W and AdSize prefix are both present. llvm-svn: 225099
* [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper2014-12-311-6/+9
| | | | | | modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [X86] Increase X86_MAX_OPERANDS from 5 to 6Adam Nemet2014-08-051-1/+1
| | | | | | | | | | | | | | | | | | | This controls the number of operands in the disassembler's x86OperandSets table. The entries describe how the operand is encoded and its type. Not to surprisingly 5 operands is insufficient for AVX512. Consider VALIGNDrrik in the next patch. These are its operand specifiers: { /* 328 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM512 }, { ENCODING_WRITEMASK, TYPE_VK8 }, { ENCODING_VVVV, TYPE_XMM512 }, { ENCODING_RM_CD64, TYPE_XMM512 }, { ENCODING_IB, TYPE_IMM8 }, }, llvm-svn: 214889
* [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov2014-07-211-1/+5
| | | | | | | | | | | | Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-171-0/+15
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-281-1/+1
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. llvm-svn: 207413
* More C++ification.Richard Smith2014-04-201-67/+41
| | | | llvm-svn: 206722
* Don't provide two different definitions of ModRMDecision, OpcodeDecision, ↵Richard Smith2014-04-201-31/+0
| | | | | | and ContextDecision in different source files (depending on #define magic). llvm-svn: 206720
* Don't define llvm::X86Disassembler::InstructionSpecifier in different ways inRichard Smith2014-04-201-9/+0
| | | | | | different source files. llvm-svn: 206719
* What year is it! This file has no reason to be written in C, and has doubly noRichard Smith2014-04-201-38/+39
| | | | | | | | | | reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. llvm-svn: 206717
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-9/+3
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-1/+6
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-1/+6
| | | | llvm-svn: 199803
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-201-2/+0
| | | | | | | | | | The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-0/+2
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-3/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-011-2/+1
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-011-4/+3
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-311-1/+2
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-301-2/+1
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-43/+49
| | | | llvm-svn: 198013
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-0/+1
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-1/+49
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-1/+10
| | | | llvm-svn: 191874
* Various x86 disassembler fixes.Craig Topper2013-09-301-4/+4
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-2/+104
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-131-0/+5
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-011-1/+0
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Tidy up trailing whitespaceCraig Topper2012-07-311-12/+12
| | | | llvm-svn: 161026
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+1
| | | | llvm-svn: 153935
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-041-3/+3
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-2/+6
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-0/+3
| | | | llvm-svn: 150167
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-1/+2
| | | | llvm-svn: 143895
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-0/+3
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-1/+1
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-0/+3
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-1/+7
| | | | llvm-svn: 128826
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-2/+19
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Merge System into Support.Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120298
* add basic avx support to the disassembler, also teach it about ssmem/sdmemChris Lattner2010-09-291-0/+1
| | | | | | | | | | operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' llvm-svn: 115019
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