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| author | Adam Nemet <anemet@apple.com> | 2014-08-05 17:23:01 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@apple.com> | 2014-08-05 17:23:01 +0000 |
| commit | 4688a2e5cbd722584b063acb31136e8dae3276d3 (patch) | |
| tree | 48236b1dd84f5e040ee942f9c41a9fa2c0dbdb7e /llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h | |
| parent | 164b07fbfe7c8f93cce055a941ff83bc76920ffc (diff) | |
| download | bcm5719-llvm-4688a2e5cbd722584b063acb31136e8dae3276d3.tar.gz bcm5719-llvm-4688a2e5cbd722584b063acb31136e8dae3276d3.zip | |
[X86] Increase X86_MAX_OPERANDS from 5 to 6
This controls the number of operands in the disassembler's x86OperandSets
table. The entries describe how the operand is encoded and its type.
Not to surprisingly 5 operands is insufficient for AVX512. Consider
VALIGNDrrik in the next patch. These are its operand specifiers:
{ /* 328 */
{ ENCODING_DUP, TYPE_DUP1 },
{ ENCODING_REG, TYPE_XMM512 },
{ ENCODING_WRITEMASK, TYPE_VK8 },
{ ENCODING_VVVV, TYPE_XMM512 },
{ ENCODING_RM_CD64, TYPE_XMM512 },
{ ENCODING_IB, TYPE_IMM8 },
},
llvm-svn: 214889
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h')
| -rw-r--r-- | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h index 13a7b557b44..3a6dbcd59d0 100644 --- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h +++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h @@ -500,7 +500,7 @@ enum ModifierType { }; #undef ENUM_ENTRY -static const unsigned X86_MAX_OPERANDS = 5; +static const unsigned X86_MAX_OPERANDS = 6; /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, |
