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* Replace C++ style comment with a C style comment to satisfy some of the ↵Craig Topper2013-10-031-1/+1
| | | | | | build bots. llvm-svn: 191880
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-34/+138
| | | | llvm-svn: 191874
* Remove 0 as a valid encoding for the m-mmmm field.Craig Topper2013-10-011-2/+0
| | | | llvm-svn: 191732
* Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-011-16/+0
| | | | llvm-svn: 191731
* Various x86 disassembler fixes.Craig Topper2013-09-301-36/+0
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Build fixRichard Mitton2013-08-301-1/+1
| | | | llvm-svn: 189699
* Fixed a bug where diassembling an instruction that had a prefix would cause ↵Richard Mitton2013-08-301-7/+9
| | | | | | LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+2
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-201-0/+21
| | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490
* X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi2013-03-251-1/+1
| | | | llvm-svn: 177910
* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
| | | | llvm-svn: 177909
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-7/+20
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Fix typoJoerg Sonnenberger2012-10-291-2/+2
| | | | llvm-svn: 166945
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-131-0/+4
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-051-3/+3
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-1/+1
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-011-7/+9
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+3
| | | | llvm-svn: 153935
* C files in llvm still have to be C89 compliant, remove C++-style comments.Benjamin Kramer2012-03-101-4/+6
| | | | llvm-svn: 152495
* Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby2012-03-091-0/+7
| | | | | | | prefix. Added a FIXME to remind us this still does not work when it is not the first prefix. llvm-svn: 152414
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-0/+2
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-231-0/+2
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-3/+1
| | | | llvm-svn: 150918
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Don't mix declarations and code.Benjamin Kramer2012-02-111-7/+5
| | | | llvm-svn: 150305
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-111-4/+9
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-0/+4
| | | | llvm-svn: 150167
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-091-5/+4
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. llvm-svn: 150161
* Persuade GCC that there is nothing worth warning about here (there isn't).Duncan Sands2012-02-051-1/+1
| | | | llvm-svn: 149834
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-3/+0
| | | | llvm-svn: 147855
* Silence warnings of a mysterious compiler that still defaults to C89.Benjamin Kramer2012-01-041-2/+2
| | | | llvm-svn: 147553
* X86Disassembler: Fix undefined behavior found by GCC 4.6Benjamin Kramer2012-01-011-3/+5
| | | | llvm-svn: 147404
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-301-0/+10
| | | | llvm-svn: 147368
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-4/+7
| | | | llvm-svn: 143895
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-68/+0
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Change C++ style comments to C style comments in X86 disassembler. Patch ↵Craig Topper2011-10-051-2/+2
| | | | | | from Joe Abbey. llvm-svn: 141162
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-6/+36
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to ↵Craig Topper2011-10-031-0/+3
| | | | | | registers xmm8-xmm15 outside 64-bit mode. llvm-svn: 140997
* Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.Craig Topper2011-10-031-9/+13
| | | | llvm-svn: 140993
* Special case disassembler handling of REX.B prefix on NOP instruction to ↵Craig Topper2011-10-021-2/+39
| | | | | | decode as XCHG R8D, EAX instead. Fixes PR10344. llvm-svn: 140971
* Fix VEX decoding in i386 mode. Fixes PR11008.Craig Topper2011-09-261-2/+2
| | | | llvm-svn: 140515
* Only disassembler instructions with vvvv != 1111 if the instruction actually ↵Craig Topper2011-09-131-4/+13
| | | | | | uses the vvvv field to encode an operand. Fixes PR10851. llvm-svn: 139591
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-0/+30
| | | | llvm-svn: 128826
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-27/+222
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Silence enum conversion warnings.Benjamin Kramer2011-02-271-2/+2
| | | | llvm-svn: 126578
* Fixed a bug in the disassembler where the mandatory 0x66Sean Callanan2011-02-021-0/+1
| | | | | | | | prefix would be misinterpreted in some cases on 32-bit x86 platforms. Thanks to Olivier Meurant for identifying the bug. llvm-svn: 124709
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Correctly disassemble truncated asm.Rafael Espindola2011-01-061-2/+4
| | | | | | Patch by Richard Simth. llvm-svn: 122962
* Make the disassembler tables const so they end up in read-only memory.Benjamin Kramer2010-10-231-7/+7
| | | | llvm-svn: 117206
* Remove a define which is never referenced.Chandler Carruth2010-10-231-6/+0
| | | | llvm-svn: 117202
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