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* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-17/+12
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* Remove trailing whitespace.Craig Topper2013-08-241-1/+1
| | | | llvm-svn: 189178
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+5
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-201-0/+9
| | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-97/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-6/+0
| | | | llvm-svn: 170578
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+1
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-051-5/+5
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-311-0/+2
| | | | llvm-svn: 162999
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-011-4/+3
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Fix a bug in the x86 disassembler's symbolic disassembly support for Jcc-JumpKevin Enderby2012-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | if Condition Is Met instuctions that was not correctly determining the target instruction. So for a jne rel32 instruction: % cat x.s .byte 0x0f, 0x85, 0x09, 0x00, 0x00, 0x00 % as x.s it was incorrectly deterining the target: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xd and with the fix it gets this correct as: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xf rdar://11505997 llvm-svn: 160694
* Remove tabs.Bill Wendling2012-07-191-9/+9
| | | | llvm-svn: 160477
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-10/+18
| | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 llvm-svn: 159402
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-1/+26
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Fixed the llvm-mv X86 disassembler so the 'C' API gets jumps properlyKevin Enderby2012-04-181-2/+5
| | | | | | | symbolicated. These have and operand type of TYPE_RELv which was not handled as isBranch in translateImmediate() in X86Disassembler.cpp. rdar://11268426 llvm-svn: 155074
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-041-1/+1
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* Added annotations for x86 pc relative loads to llvm's 'C' disassembler.Kevin Enderby2012-02-291-0/+24
| | | | | | | So with darwin's otool(1) an x86_64 hello world .o file will print: leaq L_.str(%rip), %rax ## literal pool for: Hello world llvm-svn: 151769
* Make MemoryObject accessor members const againDerek Schuff2012-02-291-1/+1
| | | | llvm-svn: 151687
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-231-18/+159
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Make the EDis tables const.Benjamin Kramer2012-02-111-1/+1
| | | | llvm-svn: 150304
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-111-8/+20
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
* Enable streaming of bitcodeDerek Schuff2012-02-061-1/+1
| | | | | | | This CL delays reading of function bodies from initial parse until materialization, allowing overlap of compilation with bitcode download. llvm-svn: 149918
* Remove mode specific disassembler classes and just call ↵Craig Topper2011-12-211-8/+2
| | | | | | X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. llvm-svn: 147046
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+6
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* X86Disassembler: if verbose logging is going to nulls(), disable logging ↵Benjamin Kramer2011-09-211-1/+5
| | | | | | | | completely. Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it. llvm-svn: 140276
* Don't attach annotations to MCInst's. Instead, have the disassembler ↵Owen Anderson2011-09-151-1/+2
| | | | | | return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. llvm-svn: 139876
* Make disassembling of VBLEND* print immediate as a XMM/YMM register name. ↵Craig Topper2011-09-141-0/+6
| | | | | | Fixes PR10917. llvm-svn: 139690
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-6/+7
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Change X86 disassembly to print immediates values as signed by default. SpecialKevin Enderby2011-09-021-0/+34
| | | | | | case those instructions that the immediate is not sign-extend. radr://8795217 llvm-svn: 139028
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson2011-08-171-7/+8
| | | | | | | | instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+2
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-0/+5
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Fixed a bug in the X86 disassembler where a member of theSean Callanan2011-02-211-4/+4
| | | | | | | | X86 instruction decode structure was being interpreted as being in units of bits, although it is actually stored in units of bytes. llvm-svn: 126147
* Make the disassembler tables const so they end up in read-only memory.Benjamin Kramer2010-10-231-9/+6
| | | | llvm-svn: 117206
* my work on adding segment registers to LEA missed the Chris Lattner2010-07-131-12/+3
| | | | | | | disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. llvm-svn: 108226
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+1
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Fixed a sign-extension bug in the X86 disassemblerSean Callanan2010-05-051-3/+55
| | | | | | | | that was causing PC-relative branch targets to be evaluated incorrectly. Also added support for checking operand values to the llvm-mc tester. llvm-svn: 103128
* Fixed a nasty layering violation in the edis sourceSean Callanan2010-04-131-0/+6
| | | | | | | | | | | | | | | code. It used to #include the enhanced disassembly information for the targets it supported straight out of lib/Target/{X86,ARM,...} but now it uses a new interface provided by MCDisassembler, and (so far) implemented by X86 and ARM. Also removed hacky #define-controlled initialization of targets in edis. If clients only want edis to initialize a limited set of targets, they can set --enable-targets on the configure command line. llvm-svn: 101179
* Fixes to the X86 disassembler. The disassembler will nowSean Callanan2010-04-021-63/+96
| | | | | | | return an error status in all failure cases, printing messages to debugs() only when debugging is enabled. llvm-svn: 100229
* TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.Daniel Dunbar2010-03-201-2/+2
| | | | llvm-svn: 99097
* Fixes to the X86 disassembler:Sean Callanan2009-12-221-5/+16
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Include based on the current path, since we already -I the X86 target's ↵Douglas Gregor2009-12-221-1/+1
| | | | | | path. Fixes CMake build llvm-svn: 91908
* Fixed library dependencies between the X86 disassembler andSean Callanan2009-12-221-8/+5
| | | | | | X86 codegen that were causing circular symbol dependencies. llvm-svn: 91871
* #if 0 out X86 disassembler for now, it is breaking the build in multiple places.Daniel Dunbar2009-12-191-0/+7
| | | | llvm-svn: 91778
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-3/+435
| | | | | | | | | | | | | | | | | | | | incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
* Sketch structure for X86 disassembler.Daniel Dunbar2009-11-251-0/+29
llvm-svn: 89850
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