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path: root/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-2/+5
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used ↵Craig Topper2012-03-291-12/+13
| | | | | | with 'v' version of instructions. llvm-svn: 153636
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Change the X86 assembler to not require a segment register on stringKevin Enderby2012-03-131-4/+5
| | | | | | | instruction's destination operand like it does for the source operand. Also fix a typo in the comment for X86AsmParser::isSrcOp(). llvm-svn: 152654
* Added a missing error check for X86 assembly with mismatched base and indexKevin Enderby2012-03-121-0/+19
| | | | | | registers not both being 64-bit or both being 32-bit registers. llvm-svn: 152580
* Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby2012-03-091-1/+3
| | | | llvm-svn: 152443
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-1/+0
| | | | llvm-svn: 150918
* Add assembler dialect attribute in asm parser which lets target specific asm ↵Devang Patel2012-01-311-4/+3
| | | | | | parser change dialect on the fly. llvm-svn: 149396
* Intel syntax. Adjust special code, used to recognize cmp<comparison ↵Devang Patel2012-01-301-2/+4
| | | | | | code>{ss,sd,ps,pd}, for intel syntax. llvm-svn: 149291
* Intel syntax. Support .intel_syntax directive.Devang Patel2012-01-301-10/+24
| | | | llvm-svn: 149270
* Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]Devang Patel2012-01-271-3/+5
| | | | llvm-svn: 149142
* Keep source location information for X86 MCFixup's.Jim Grosbach2012-01-271-0/+3
| | | | llvm-svn: 149106
* Intel Syntax: Extend special hand coded logic, to recognize special ↵Devang Patel2012-01-241-5/+15
| | | | | | instructions, for intel syntax. llvm-svn: 148864
* Fix typo. Devang Patel2012-01-231-1/+1
| | | | llvm-svn: 148751
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+7
| | | | llvm-svn: 148737
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-6/+16
| | | | llvm-svn: 148721
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-4/+16
| | | | llvm-svn: 148712
* Remove unused variables.Benjamin Kramer2012-01-211-2/+0
| | | | llvm-svn: 148635
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-28/+16
| | | | llvm-svn: 148591
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-0/+5
| | | | llvm-svn: 148570
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+78
| | | | llvm-svn: 148489
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-1/+1
| | | | | | displacement. llvm-svn: 148486
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+114
| | | | | | if available. llvm-svn: 148485
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-16/+87
| | | | | | more desirable. llvm-svn: 148431
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+4
| | | | llvm-svn: 148334
* Untabify.Devang Patel2012-01-171-12/+12
| | | | llvm-svn: 148322
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-2/+1
| | | | | | displacement. llvm-svn: 148321
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-51/+113
| | | | llvm-svn: 148312
* Revert r148131, it was committed before it was ready.Devang Patel2012-01-131-46/+40
| | | | llvm-svn: 148134
* Refactor.Devang Patel2012-01-131-40/+46
| | | | llvm-svn: 148131
* Rename X86ATTAsmParser -> X86AsmParserDevang Patel2012-01-121-17/+17
| | | | | | We are using one parser to parse att as well as intel style syntax. llvm-svn: 148032
* Add predicate method check match memory operand size, if available.Devang Patel2012-01-121-3/+50
| | | | | | In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
* Add intel style operand parser skeleton. Devang Patel2012-01-121-1/+97
| | | | | | This is a work in progress. llvm-svn: 148002
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-061-2/+1
| | | | llvm-svn: 143891
* Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.Benjamin Kramer2011-10-161-9/+14
| | | | | | | | <stdin>:1:12: error: register %rax is only available in 64-bit mode incl %rax ^~~~ llvm-svn: 142137
* X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and ↵Benjamin Kramer2011-10-161-3/+4
| | | | | | | | | | print ranges for invalid operands. <stdin>:1:4: error: invalid instruction mnemonic 'abc' abc incl %edi ^~~ llvm-svn: 142135
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner2011-10-161-6/+13
| | | | | | | | | | | | | | | does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. llvm-svn: 142106
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* MCTargetAsmParser target match predicate support.Jim Grosbach2011-08-151-1/+2
| | | | | | | | Allow a target assembly parser to do context sensitive constraint checking on a potential instruction match. This will be used, for example, to handle Thumb2 IT block parsing. llvm-svn: 137675
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-271-8/+15
| | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-271-0/+15
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
* Support .code32 and .code64 in X86 assembler.Evan Cheng2011-07-271-0/+27
| | | | llvm-svn: 136197
* Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng2011-07-261-7/+6
| | | | | | MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. llvm-svn: 136027
* Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng2011-07-231-2/+1
| | | | | | they belong. llvm-svn: 135833
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-3/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Update MCParsedAsmOperand debug methods.Jim Grosbach2011-07-131-1/+1
| | | | | | | | | | | Update the debug output interface for MCParsedAsmOperand to have a print() method which takes an output stream argument, an << operator which invokes the print method using the given stream, and a dump() method which prints the operand to the dbgs() stream. This makes the interface more consistent with the rest of LLVM, and more convenient to use at the debugger command line. llvm-svn: 135043
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-7/+7
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-7/+5
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.Benjamin Kramer2011-07-081-3/+4
| | | | | | Found by valgrind. llvm-svn: 134738
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