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| author | Kevin Enderby <enderby@apple.com> | 2012-03-12 21:32:09 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2012-03-12 21:32:09 +0000 |
| commit | fb3110b5d23e1a75d7166db68f5b8d018a627261 (patch) | |
| tree | a8d69f3b1bbe6533dd625626b32020bcfe30579e /llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | |
| parent | adbeb9f38d16f44c058f8cd00ed8e22d416fc5c4 (diff) | |
| download | bcm5719-llvm-fb3110b5d23e1a75d7166db68f5b8d018a627261.tar.gz bcm5719-llvm-fb3110b5d23e1a75d7166db68f5b8d018a627261.zip | |
Added a missing error check for X86 assembly with mismatched base and index
registers not both being 64-bit or both being 32-bit registers.
llvm-svn: 152580
Diffstat (limited to 'llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index e05b50c57e3..ce32c7753f9 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -838,6 +838,7 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { // If we reached here, then we just ate the ( of the memory operand. Process // the rest of the memory operand. unsigned BaseReg = 0, IndexReg = 0, Scale = 1; + SMLoc IndexLoc; if (getLexer().is(AsmToken::Percent)) { SMLoc StartLoc, EndLoc; @@ -851,6 +852,7 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { if (getLexer().is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. + IndexLoc = Parser.getTok().getLoc(); // Following the comma we should have either an index register, or a scale // value. We don't support the later form, but we want to parse it @@ -912,6 +914,23 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { SMLoc MemEnd = Parser.getTok().getLoc(); Parser.Lex(); // Eat the ')'. + // If we have both a base register and an index register make sure they are + // both 64-bit or 32-bit registers. + if (BaseReg != 0 && IndexReg != 0) { + if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) && + !X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) && + IndexReg != X86::RIZ) { + Error(IndexLoc, "index register is 32-bit, but base register is 64-bit"); + return 0; + } + if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) && + !X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) && + IndexReg != X86::EIZ){ + Error(IndexLoc, "index register is 64-bit, but base register is 32-bit"); + return 0; + } + } + return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, MemStart, MemEnd); } |

