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* [MC,X86] Cleanup some X86 parser functions to use MCParser helpers. NFCI.Nirav Dave2018-03-201-45/+22
| | | | llvm-svn: 328019
* [X86] Added support for nocf_check attribute for indirect Branch TrackingOren Ben Simhon2018-03-171-3/+4
| | | | | | | | | | | | | | | X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET). IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp. The `nocf_check` attribute has two roles in the context of X86 IBT technology: 1. Appertains to a function - do not add ENDBR instruction at the beginning of the function. 2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction. This patch implements `nocf_check` context for Indirect Branch Tracking. It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks. Differential Revision: https://reviews.llvm.org/D41879 llvm-svn: 327767
* MC intel asm parser: Allow @ at the start of function names.Nico Weber2018-03-121-1/+5
| | | | | | | | Ports parts of r193000 to the intel parser. Fixes part of PR36676. https://reviews.llvm.org/D44359 llvm-svn: 327262
* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-021-83/+73
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* Allow usage of X86-prefixes as separate instrs.Andrew V. Tischenko2018-01-171-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D42102 llvm-svn: 322623
* [X86] When parsing rounding mode operands, provide a proper end location so ↵Craig Topper2018-01-061-5/+6
| | | | | | we don't crash when trying to print an error message using it. llvm-svn: 321930
* It's a fix for Bug 35741 - can't use comments after x86 prefixes.Andrew V. Tischenko2017-12-261-2/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D41579 llvm-svn: 321459
* [X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.Craig Topper2017-12-021-13/+25
| | | | llvm-svn: 319612
* Add -print-schedule scheduling comments to inline asm.Andrew V. Tischenko2017-11-091-2/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
* [X86] Don't call validateInstruction from MatchAndEmitInstruction when ↵Craig Topper2017-11-081-2/+2
| | | | | | | | MatchingInlineAsm is set. The MCInst won't be populated. Without this we can't parse gather instructions in ms inline asm blocks. The validateInstruction function was introduced in r316700 to check gather constraints. llvm-svn: 317713
* [X86][AsmParser] Treat '%' as the modulo operator under Intel syntaxReid Kleckner2017-10-311-0/+1
| | | | | | | | | | It can't be a register prefix, anyway. This is consistent with the masm docs on MSDN: https://msdn.microsoft.com/en-us/library/t4ax90d2.aspx This is a straight-forward extension of our support for "MOD" implemented in https://reviews.llvm.org/D33876 / r306425 llvm-svn: 317011
* [X86] Teach the assembly parser to warn on duplicate registers in gather ↵Craig Topper2017-10-261-0/+71
| | | | | | | | | | instructions. Fixes PR32238. Differential Revision: https://reviews.llvm.org/D39077 llvm-svn: 316700
* [X86] Use correct type for return value of ComputeAvailableFeatures in the ↵Craig Topper2017-10-261-1/+1
| | | | | | | | AsmParser. NFC There aren't enough used bits to make this a functional change, but we should fix it for consistency. llvm-svn: 316639
* Fix or vs || typo.Simon Pilgrim2017-10-161-1/+1
| | | | llvm-svn: 315903
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-161-10/+56
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [codeview] Implement FPO data assembler directivesReid Kleckner2017-10-111-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds a set of new directives that describe 32-bit x86 prologues. The directives are limited and do not expose the full complexity of codeview FPO data. They are merely a convenience for the compiler to generate more readable assembly so we don't need to generate tons of labels in CodeGen. If our prologue emission changes in the future, we can change the set of available directives to suit our needs. These are modelled after the .seh_ directives, which use a different format that interacts with exception handling. The directives are: .cv_fpo_proc _foo .cv_fpo_pushreg ebp/ebx/etc .cv_fpo_setframe ebp/esi/etc .cv_fpo_stackalloc 200 .cv_fpo_endprologue .cv_fpo_endproc .cv_fpo_data _foo I tried to follow the implementation of ARM EHABI CFI directives by sinking most directives out of MCStreamer and into X86TargetStreamer. This helps avoid polluting non-X86 code with WinCOFF specific logic. I used cdb to confirm that this can show locals in parent CSRs in a few cases, most importantly the one where we use ESI as a frame pointer, i.e. the one in http://crbug.com/756153#c28 Once we have cdb integration in debuginfo-tests, we can add integration tests there. Reviewers: majnemer, hans Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D38776 llvm-svn: 315513
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-2/+1
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / ↵Coby Tayree2017-09-291-60/+90
| | | | | | | | | | | immediate expressions Allow the proper recognition of Enum values and global variables inside ms inline-asm memory / immediate expressions, as they require some additional overhead and treated incorrect if doesn't early recognized. supersedes D33278, D35774 Differential Revision: https://reviews.llvm.org/D37412 llvm-svn: 314493
* [x86][AsmParser] Allow some more MS size directivesCoby Tayree2017-09-281-0/+3
| | | | | | | MS allows the following size directives: float/double and long as synonymous to dword/qword and dword, respectively. Differential Revision: https://reviews.llvm.org/D37190 llvm-svn: 314410
* [X86] Fix typo in comment. NFCCraig Topper2017-09-261-1/+1
| | | | llvm-svn: 314247
* [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).Konstantin Belochapka2017-09-221-2/+5
| | | | | | | Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value. Differential Revision: https://reviews.llvm.org/D38117 llvm-svn: 314044
* [X86][X86AsmParser] adding const on InlineAsmIdentifierInfo in ↵Coby Tayree2017-09-101-2/+2
| | | | | | CreateMemForInlineAsm. NFC. llvm-svn: 312881
* [X86AsmParser] Refactoring, (almost) NFC.Coby Tayree2017-08-241-396/+220
| | | | | | | | | | Some refactoring to X86AsmParser, mostly regarding the way rewrites are conducted. Mainly, we try to concentrate all the rewrite effort under one hood, so it'll hopefully be less of a mess and easier to maintain and understand. naturally, some frontend tests were affected: D36794 Differential Revision: https://reviews.llvm.org/D36793 llvm-svn: 311639
* [X86] Allow xacquire/xrelease prefixesCoby Tayree2017-08-211-5/+15
| | | | | | | Allow those prefixes on assembly code Differential Revision: https://reviews.llvm.org/D36845 llvm-svn: 311309
* [X86][AsmParser][AVX512] Error appropriately when K0 is tried as a write-maskCoby Tayree2017-08-131-1/+4
| | | | | | | | | K0 isn't expected as a write-mask, so provide a detailed error here, instead of the more generic one (invalid op for insn) Conforms with gas Differential Revision: https://reviews.llvm.org/D36570 llvm-svn: 310789
* [X86][Asm] Allow negative immediate to appear before bracketed expressionCoby Tayree2017-08-091-5/+0
| | | | | | | | | Currently, only non-negative immediate is allowed prior to a brac expression (memory reference). MASM / GAS does not have any problem cope with the left side of the real line, so we should be able to as well. Differntial Revision: https://reviews.llvm.org/D36229 llvm-svn: 310528
* Fix -Wpessimizing-move warning.Haojian Wu2017-08-091-2/+2
| | | | llvm-svn: 310469
* [AsmParser][AVX512]Enhance OpMask/Zero/Merge syntax check rubostnessCoby Tayree2017-08-091-4/+8
| | | | | | | | Adopt a more strict approach regarding what marks should/can appear after a destination register, when operating upon an AVX512 platform. Differential Revision: https://reviews.llvm.org/D35785 llvm-svn: 310467
* [x86][inline-asm][ms-compat] legalize the use of "jc/jz short <op>"Coby Tayree2017-07-301-1/+2
| | | | | | | | | MS ignores the keyword "short" when used after a jc/jz instruction, LLVM ought to do the same. Test: D35893 Differential Revision: https://reviews.llvm.org/D35892 llvm-svn: 309509
* Revert "This patch enables the usage of constant Enum identifiers within ↵Eric Christopher2017-07-251-55/+21
| | | | | | | | Microsoft style inline assembly statements." This reverts commit r308966. llvm-svn: 309005
* X86 Asm uses assertions instead of proper diagnostic. This patch fixes that.Andrew V. Tischenko2017-07-251-23/+57
| | | | | | Differential Revision: https://reviews.llvm.org/D35115 llvm-svn: 308972
* This patch enables the usage of constant Enum identifiers within Microsoft ↵Matan Haroush2017-07-251-21/+55
| | | | | | | | | | style inline assembly statements. Differential Revision: https://reviews.llvm.org/D33277 https://reviews.llvm.org/D33278 llvm-svn: 308966
* Revert "[X86][InlineAsm][Ms Compatibility]Prefer variable name over a ↵Reid Kleckner2017-07-241-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | register when the two collides" This reverts r308867 and r308866. It broke the sanitizer-windows buildbot on C++ code similar to the following: namespace cl { } void f() { __asm { mov al, cl } } t.cpp(4,13): error: unexpected namespace name 'cl': expected expression mov al, cl ^ In this case, MSVC parses 'cl' as a register, not a namespace. llvm-svn: 308926
* [X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when ↵Coby Tayree2017-07-241-1/+12
| | | | | | | | | | | | | | | | | | | | | the two collides On MS-style, the following snippet: int eax; __asm mov eax, ebx should yield loading of ebx, into the location pointed by the variable eax This patch sees to it. Currently, a reg-to-reg move would have been invoked. clang: D34740 Differential Revision: https://reviews.llvm.org/D34739 llvm-svn: 308866
* fix typos in comments and error messges; NFCHiroshi Inoue2017-07-131-2/+2
| | | | llvm-svn: 307885
* [X86][AsmParser][MS-compatability] Binary/Unary operators enhancementsCoby Tayree2017-06-271-37/+75
| | | | | | | | | | | Introducing MOD binary operator https://msdn.microsoft.com/en-us/library/hha180wt.aspx Enhancing unary operators NEG and NOT, to support more complex patterns Differential Revision: https://reviews.llvm.org/D33876 llvm-svn: 306425
* [inline asm] dot operator while using imm generates wrong ir + asm - llvm partMarina Yatsina2017-06-261-2/+1
| | | | | | | | | | | | | | | | | Inline asm dot operator while using imm generates wrong ir and asm This also fixes bugzilla 32987: https://bugs.llvm.org//show_bug.cgi?id=32987 The clang part of the review that contains the test can be found here: https://reviews.llvm.org/D33040 commit on behald of zizhar Differential Revision: https://reviews.llvm.org/D33039 llvm-svn: 306300
* The fix for PR22004: X86AsmParser.cpp asserts: OperandStack.size() > 1 && ↵Andrew V. Tischenko2017-05-261-2/+3
| | | | | | "Too few operands." llvm-svn: 303985
* [ms-inline-asm] Use the frontend size only for ambiguous instructionsReid Kleckner2017-05-041-65/+29
| | | | | | | | | | | | | | | | | | This avoids problems on code like this: char buf[16]; __asm { movups xmm0, [buf] mov [buf], eax } The frontend size in this case (1) is wrong, and the register makes the instruction matching unambiguous. There are also enough bytes available that we shouldn't complain to the user that they are potentially using an incorrectly sized instruction to access the variable. Supersedes D32636 and D26586 and fixes PR28266 llvm-svn: 302179
* PR31007 and PR27884 will be closed: a possibility to compile constants like ↵Andrew V. Tischenko2017-04-261-0/+2
| | | | | | 0bH is now supported in MS asm. llvm-svn: 301390
* [X86][MS-compatability]Allow named synonymous for MS-assembly operatorsCoby Tayree2017-04-041-0/+27
| | | | | | | | | | This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability MASM reference: https://msdn.microsoft.com/en-us/library/94b6khh4.aspx Differential Revision: D31277 llvm-svn: 299439
* [X86][MS-compatability][llvm] allow MS TYPE/SIZE/LENGTH operators as a part ↵Coby Tayree2017-03-211-45/+60
| | | | | | | | | | | | | | | | of a compound expression This patch introduces X86AsmParser with the ability to handle the aforementioned ops within compound "MS" arithmetical expressions. Currently - only supported as a stand alone Operand, e.g.: "TYPE X" now allowed : "4 + TYPE X * 128" Clang side: https://reviews.llvm.org/D31174 Differential Revision: https://reviews.llvm.org/D31173 llvm-svn: 298425
* Revert 292404 due to buildbot failures.Kirill Bobyrev2017-01-181-3/+3
| | | | llvm-svn: 292407
* [X86] Minor code cleanup to fix several clang-tidy warnings. NFCKirill Bobyrev2017-01-181-3/+3
| | | | llvm-svn: 292404
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-181-1/+1
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* [X86] Don't round trip a unique_ptr through a raw pointer for assignment.Benjamin Kramer2016-11-241-1/+1
| | | | | | No functional change. llvm-svn: 287888
* [AVX512][inline-asm] Fix AVX512 inline assembly instruction resolution when ↵Coby Tayree2016-11-221-3/+58
| | | | | | | | | | | | | | | | | | | | | | | | the size qualifier of a memory operand is not specified explicitly. This commit handles cases where the size qualifier of an indirect memory reference operand in Intel syntax is missing (e.g. "vaddps xmm1, xmm2, [a]"). GCC will deduce the size qualifier for AVX512 vector and broadcast memory operands based on the possible matches: "vaddps xmm1, xmm2, [a]" matches only “XMMWORD PTR” qualifier. "vaddps xmm1, xmm2, [a]{1to4}" matches only “DWORD PTR” qualifier. This is different from the current behavior of LLVM, which deduces the size qualifier based on the size of the memory operand. For "vaddps xmm1, xmm2, [a]" "char a;" will imply "BYTE PTR" qualifier "short a;" will imply "WORD PTR" qualifier. This commit aligns LLVM to GCC’s behavior. This is the LLVM part of the review. The Clang part of the review: https://reviews.llvm.org/D26587 Differential Revision: https://reviews.llvm.org/D26586 llvm-svn: 287630
* small fixup which enables the issuing of the aforementioned instruction (w/o ↵Coby Tayree2016-11-211-1/+1
| | | | | | | | operands), on MS/Intel syntax. Differential Revision: https://reviews.llvm.org/D26913 llvm-svn: 287548
* [X86][InlineAsm]Test commit.Coby Tayree2016-11-201-1/+1
| | | | | | | | Fixing a wrong comment on X86AsmParser.cpp::ParseZ: "true" --> "false" Differential Revision: https://reviews.llvm.org/D26797 llvm-svn: 287484
* [x86][inline-asm][avx512] allow swapping of '{k<num>}' & '{z}' marksMichael Zuckerman2016-10-181-25/+65
| | | | | | | | | | | | | | | | | | | | | | | Committing on behalf of Coby Tayree: After check-all and LGTM Desc: AVX512 allows dest operand to be followed by an op-mask register specifier ('{k<num>}', which in turn may be followed by a merging/zeroing specifier ('{z}') Currently, the following forms are allowed: {k<num>} {k<num>}{z} This patch allows the following forms: {z}{k<num>} and ignores the next form: {z} Justification would be quite simple - GCC Differential Revision: http://reviews.llvm.org/D25013 llvm-svn: 284479
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