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author | Coby Tayree <coby.tayree@intel.com> | 2017-04-04 14:43:23 +0000 |
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committer | Coby Tayree <coby.tayree@intel.com> | 2017-04-04 14:43:23 +0000 |
commit | 2cb497afa46a0c6fe8ed6c5793e59d9e0b054a68 (patch) | |
tree | f62568e7f0bb57aa0b592321842866218f81f38e /llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | |
parent | 448222d8bad122e857df2356ae15b2a5c12b2590 (diff) | |
download | bcm5719-llvm-2cb497afa46a0c6fe8ed6c5793e59d9e0b054a68.tar.gz bcm5719-llvm-2cb497afa46a0c6fe8ed6c5793e59d9e0b054a68.zip |
[X86][MS-compatability]Allow named synonymous for MS-assembly operators
This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx
Differential Revision: D31277
llvm-svn: 299439
Diffstat (limited to 'llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp')
-rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index a596ea00825..324da650e74 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -717,6 +717,7 @@ private: std::unique_ptr<X86Operand> ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size); std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End); + bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM); bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End); std::unique_ptr<X86Operand> ParseIntelBracExpression(unsigned SegReg, SMLoc Start, int64_t ImmDisp, @@ -1298,6 +1299,30 @@ RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> &AsmRewrites, } } +// Some binary bitwise operators have a named synonymous +// Query a candidate string for being such a named operator +// and if so - invoke the appropriate handler +bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) { + // A named operator should be either lower or upper case, but not a mix + if (Name.compare(Name.lower()) && Name.compare(Name.upper())) + return false; + if (Name.equals_lower("not")) + SM.onNot(); + else if (Name.equals_lower("or")) + SM.onOr(); + else if (Name.equals_lower("shl")) + SM.onLShift(); + else if (Name.equals_lower("shr")) + SM.onRShift(); + else if (Name.equals_lower("xor")) + SM.onXor(); + else if (Name.equals_lower("and")) + SM.onAnd(); + else + return false; + return true; +} + bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -1339,6 +1364,8 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { UpdateLocLex = false; if (TK != AsmToken::String && !ParseRegister(TmpReg, IdentLoc, End)) { SM.onRegister(TmpReg); + } else if (ParseIntelNamedOperator(Identifier, SM)) { + UpdateLocLex = true; } else if (!isParsingInlineAsm()) { if (getParser().parsePrimaryExpr(Val, End)) return Error(Tok.getLoc(), "Unexpected identifier!"); |