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* [WebAssembly] Handle undefined lane indices in SIMD patternsThomas Lively2018-10-192-2/+40
| | | | | | | | | | | | | | | | Summary: Undefined indices in shuffles can be used when not all lanes of the output vector will be used. This happens for example in the expansion of vector reduce operations. Regardless, undefs are legal as lane indices in IR and should be supported. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53057 llvm-svn: 344803
* Revert "[WebAssembly] LSDA info generation"Krasimir Georgiev2018-10-163-21/+3
| | | | | | | | This reverts commit r344575. Newly introduced test eh-lsda.ll.test fails with use-after-free under ASAN build. llvm-svn: 344639
* [WebAssembly] LSDA info generationHeejin Ahn2018-10-163-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds support for LSDA (exception table) generation for wasm EH. Wasm EH mostly follows the structure of Itanium-style exception tables, with one exception: a call site table entry in wasm EH corresponds to not a call site but a landing pad. In wasm EH, the VM is responsible for stack unwinding. After an exception occurs and the stack is unwound, the control flow is transferred to wasm 'catch' instruction by the VM, after which the personality function is called from the compiler-generated code. (Refer to WasmEHPrepare pass for more information on this part.) This patch: - Changes wasm.landingpad.index intrinsic to take a token argument, to make this 1:1 match with a catchpad instruction - Stores landingpad index info and catch type info MachineFunction in before instruction selection - Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an exception table - Adds WasmException class with overridden methods for table generation - Adds support for LSDA section in Wasm object writer Reviewers: dschuff, sbc100, rnk Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52748 llvm-svn: 344575
* [TI removal] Make variables declared as `TerminatorInst` and initializedChandler Carruth2018-10-151-1/+1
| | | | | | | | | | | | | by `getTerminator()` calls instead be declared as `Instruction`. This is the biggest remaining chunk of the usage of `getTerminator()` that insists on the narrow type and so is an easy batch of updates. Several files saw more extensive updates where this would cascade to requiring API updates within the file to use `Instruction` instead of `TerminatorInst`. All of these were trivial in nature (pervasively using `Instruction` instead just worked). llvm-svn: 344502
* Move some helpers from the global namespace into anonymous ones.Benjamin Kramer2018-10-131-1/+1
| | | | llvm-svn: 344468
* [WebAssembly][NFC] Fix signed/unsigned comparison warningThomas Lively2018-10-131-1/+3
| | | | llvm-svn: 344459
* [WebAssembly] SIMD min and maxThomas Lively2018-10-131-7/+7
| | | | | | | | | | | | Summary: Depends on D52324 and D52764. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52325 llvm-svn: 344438
* [WebAssembly][NFC] Unify ARGUMENT classesThomas Lively2018-10-135-45/+36
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53172 llvm-svn: 344436
* [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS] (fixed)Thomas Lively2018-10-1111-95/+5
| | | | llvm-svn: 344287
* [WebAssembly] Revert rL344180, which was breaking expensive checksThomas Lively2018-10-1111-3/+94
| | | | llvm-svn: 344280
* [WebAssembly][NFC] Use intrinsic dag nodes directlyThomas Lively2018-10-113-70/+14
| | | | | | | | | | | | Summary: Instead of custom lowering to WebAssemblyISD nodes first. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53119 llvm-svn: 344211
* [WebAssembly] Saturating float to int intrinsicsThomas Lively2018-10-112-0/+28
| | | | | | | | | | | | | | | | Summary: Although the saturating float to int instructions are already emitted from normal IR, the fpto{s,u}i instructions produce poison values if the argument cannot fit in the result type. These intrinsics are therefore necessary to get guaranteed defined saturating behavior. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53004 llvm-svn: 344204
* [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS]Thomas Lively2018-10-1011-90/+3
| | | | | | | | | | | | | Summary: By moving that line into the `I` multiclass. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53093 llvm-svn: 344180
* [WebAssembly][NFC] Use vnot patfrag to simplify v128.notThomas Lively2018-10-101-14/+7
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53097 llvm-svn: 344175
* [WebAssembly] Fix fneg loweringThomas Lively2018-10-101-28/+13
| | | | | | | | | | | | | | Summary: Subtraction from zero and floating point negation do not have the same semantics, so fix lowering. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52948 llvm-svn: 344107
* [WebAssembly] Improve comments for SIMD instruction definitionsHeejin Ahn2018-10-101-2/+2
| | | | llvm-svn: 344106
* [WebAssembly] Handle V128 register class in explicit locals passThomas Lively2018-10-091-0/+2
| | | | | | | | | | | | | | Summary: Also add tests to catch crashes in passes that are not normally run in tests. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52959 llvm-svn: 344094
* [WebAssembly] Improve readability of SIMD instructions (NFC)Heejin Ahn2018-10-093-442/+586
| | | | | | | | | | | | | | | | Summary: - Categorize instructions into the categories as in the SIMD spec - Move SIMD-related definition to WebAssemblyInstrSIMD.td - Put definition and use of patterns together - Add newlines here and there Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53045 llvm-svn: 344086
* [WebAssembly] Saturating arithmetic intrinsicsThomas Lively2018-10-053-0/+45
| | | | | | | | | | | | Summary: Depends on D52805. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52813 llvm-svn: 343833
* [WebAssembly] Ignore DBG_VALUE in WebAssemblyCFGStackify pass when looking ↵Yury Delendik2018-10-041-0/+4
| | | | | | | | | | | | | | | | | | | for block start Summary: Fixes https://bugs.llvm.org/show_bug.cgi?id=39158 and regression caused by D49034. Though it is possible the problem was existed before and was exposed by additional DBG_VALUEs. Reviewers: sunfish, dschuff, aheejin Reviewed By: aheejin Subscribers: sbc100, aheejin, llvm-commits, alexcrichton, jgravelle-google Differential Revision: https://reviews.llvm.org/D52837 llvm-svn: 343827
* [WebAssembly] Don't modify preds/succs iterators while erasing from themHeejin Ahn2018-10-041-4/+7
| | | | | | | | | | | | | | Summary: This caused out-of-bound bugs. Found by `-DLLVM_ENABLE_EXPENSIVE_CHECKS=ON`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52902 llvm-svn: 343814
* Fix MSVC "not all control paths return a value" warning. NFCI.Simon Pilgrim2018-10-041-0/+1
| | | | llvm-svn: 343765
* [WebAssembly] Bitselect intrinsic and instructionThomas Lively2018-10-033-0/+31
| | | | | | | | | | | | Summary: Depends on D52755. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52805 llvm-svn: 343739
* [WebAssembly] Refactor WasmSignature and use it for MCSymbolWasmDerek Schuff2018-10-0310-118/+106
| | | | | | | | | | | | MCContext does not destroy MCSymbols on shutdown. So, rather than putting SmallVectors (which may heap-allocate) inside MCSymbolWasm, use unowned pointer to a WasmSignature instead. The signatures are now owned by the AsmPrinter. Also uses WasmSignature instead of param and result vectors in TargetStreamer, and leaves some TODOs for further simplification. Differential Revision: https://reviews.llvm.org/D52580 llvm-svn: 343733
* [WebAssembly] any_true and all_true intrinsics and instructionsThomas Lively2018-10-033-3/+31
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52755 llvm-svn: 343649
* [WebAssembly] Stop generating helper functions in ↵Sam Clegg2018-10-021-85/+17
| | | | | | | | | | | | | | | | | | | | | | | | | WebAssemblyLowerEmscriptenEHSjLj Previously we were creating weakly defined helper function in each translation unit: - setThrew - setTempRet0 Instead we now assume these will be provided at link time. In emscripten they are provided in compiler-rt: https://github.com/kripken/emscripten/pull/7203 Additionally we previously created three global variable which are also now required to exist at link time instead. - __THREW__ - _threwValue - __tempRet0 Differential Revision: https://reviews.llvm.org/D49208 llvm-svn: 343640
* [WebAssembly] Restore slashes in SIMD conversion namesThomas Lively2018-10-021-8/+8
| | | | | | | | | | | | Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
* [WebAssembly] Fixed AsmParser not allowing instructions with /Wouter van Oortmerssen2018-10-011-9/+28
| | | | | | | | | | | | | | | | | | | Summary: The AsmParser Lexer regards these as a seperate token. Here we expand the instruction name with them if they are adjacent (no whitespace). Tested: the basic-assembly.s test case has one case with a / in it. The currently are also instructions with : in them, which we intend to rename rather than fix them here. Reviewers: tlively, dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52442 llvm-svn: 343501
* WebAssembly: Rename GetSignature to GetLibcallSignature [NFC]Derek Schuff2018-09-273-16/+19
| | | | llvm-svn: 343275
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-271-10/+9
| | | | | | | | | | | | Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
* [WebAssembly] Fix MRI.hasOneNonDBGUse assert in WebAssemblyRegStackify pass Yury Delendik2018-09-261-2/+2
| | | | | | | | | | | | | | | | | Summary: The OneUseDominatesOtherUses in the WebAssemblyRegStackify not properly validates register use using hasOneUse. Since we added/modified DBG_VALUE the assert started catching valid cases. See also https://reviews.llvm.org/D49034#1247200 Fix verified by running the wasm waterfall. Reviewed By: dschuff Tags: #debug-info Differential Revision: https://reviews.llvm.org/D49034 llvm-svn: 343154
* [WebAssembly] SIMD conversionsThomas Lively2018-09-261-0/+16
| | | | | | | | | | | | | | | | Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
* [WebAssembly] Move/clone DBG_VALUE during WebAssemblyRegStackify passYury Delendik2018-09-251-0/+59
| | | | | | | | | | | | | | | | | | Summary: The MoveForSingleUse or MoveAndTeeForMultiUse functions move wasm instructions, however DBG_VALUE stay unchanged -- moving or cloning these. Reviewers: dschuff Reviewed By: dschuff Subscribers: mattd, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits, aardappel Tags: #debug-info Differential Revision: https://reviews.llvm.org/D49034 llvm-svn: 343007
* [WebAssembly] SIMD sqrtThomas Lively2018-09-251-0/+9
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52387 llvm-svn: 342937
* [WebAssembly] Simplified selecting asmmatcher stack instructions.Wouter van Oortmerssen2018-09-212-0/+3
| | | | | | | | | | | | | | | | Summary: By using the existing isCodeGenOnly bit in the tablegen defs, as suggested by tlively in https://reviews.llvm.org/D51662 Tested: llvm-lit -v `find test -name WebAssembly` Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52373 llvm-svn: 342772
* [WebAssembly] Add V128 value type to binary formatThomas Lively2018-09-205-23/+15
| | | | | | | | | | | | | | Summary: Adds the necessary support to lib/ObjectYAML and fixes SIMD calls to allow the tests to work. Also removes some dead code that would otherwise have to have been updated. Reviewers: aheejin, dschuff, sbc100 Subscribers: jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52105 llvm-svn: 342689
* [WebAssembly] Renumber SIMD opsThomas Lively2018-09-201-35/+35
| | | | | | | | | | | | | | | Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
* [WebAssembly][NFC] Remove extra space in WebAssemblyInstrSIMD.tdThomas Lively2018-09-191-1/+1
| | | | llvm-svn: 342522
* [WebAssembly] v4f32.abs and v2f64.absThomas Lively2018-09-181-0/+8
| | | | | | | | | | Summary: implement lowering of @llvm.fabs for vector types. Reviewers: aheejin, dschuff Subscribers: llvm-svn: 342513
* [WebAssembly] SIMD shiftsThomas Lively2018-09-151-0/+26
| | | | | | | | | | | | | | | | | Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
* [WebAssembly] SIMD negThomas Lively2018-09-141-0/+30
| | | | | | | | | | | | Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
* [WebAssembly] Fix signature of `main` in FixFunctionBitcastsSam Clegg2018-09-131-2/+4
| | | | | | | | | Also, add a check to ensure that when main has the expected signature we do not create a wrapper. Differential Revision: https://reviews.llvm.org/D51562 llvm-svn: 342157
* Remove isAsCheapAsAMove from v128.constThomas Lively2018-09-131-1/+1
| | | | llvm-svn: 342106
* Remove isAsCheapAsAMove from mem opsThomas Lively2018-09-131-2/+2
| | | | llvm-svn: 342105
* [WebAssembly] Add missing SIMD instruction attributesThomas Lively2018-09-131-2/+3
| | | | | | | | | | | | | | Summary: These attributes are copied from equivalent instructions in WebAssemblyInstrInfo.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51518 llvm-svn: 342104
* [WebAssembly] Make tied inline asm operands work againHeejin Ahn2018-09-121-0/+5
| | | | | | | | | | | | | | | | | Summary: rL341389 broke code with tied register operands in inline assembly. For example, `asm("" : "=r"(var) : "0"(var));` The code above specifies the input operand to be in the same register with the output operand, tying the two register. This patch makes this kind of code work again. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, eraman, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51991 llvm-svn: 342084
* [WebAssembly] SIMD comparisonsThomas Lively2018-09-122-1/+55
| | | | | | | | | | | | | | | | Summary: Match the ordering semantics of non-vector comparisons. For floating point comparisons that do not correspond to instructions, the tests check that some vector comparison instruction was emitted but do not care about the full implementation. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51765 llvm-svn: 342064
* [Target] Untangle disassemblersBenjamin Kramer2018-09-101-1/+0
| | | | | | | Disassemblers cannot depend on main target headers. The same is true for MCTargetDesc, but there's a lot more cleanup needed for that. llvm-svn: 341822
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-074-0/+95
| | | | | | | | | | | | | | | | | | Summary: Since the shuffle mask is not exposed as an operand in the native ISel DAG, create a new WebAssembly ISD node exposing the mask. The mask is lowered as sixteen immediate byte indices no matter what type the original vector shuffle was operating on. This CL depends on D51656 Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51659 llvm-svn: 341718
* [WebAssembly] Change SIMD lane indices to vec_i8imm_opThomas Lively2018-09-071-4/+4
| | | | | | | | | | | | Summary: To explicitly opt out of LEB encoding for these immediates. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51766 llvm-svn: 341707
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