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* [WebAssembly] Optimize away return instructions using fallthroughs.Dan Gohman2016-05-211-3/+3
| | | | | | | | | This saves a small amount of code size, and is a first small step toward passing values on the stack across block boundaries. Differential Review: http://reviews.llvm.org/D20450 llvm-svn: 270294
* [WebAssembly] Update WebAssembly target for r269988.Dan Gohman2016-05-191-3/+10
| | | | llvm-svn: 270017
* Factor PrologEpilogInserter around spilling, frame finalization, and scavengingDerek Schuff2016-05-171-8/+0
| | | | | | | | | | | | | | | PrologEpilogInserter has these 3 phases, which are related, but not all of them are needed by all targets. This patch reorganizes PEI's varous functions around those phases for more clear separation. It also introduces a new TargetMachine hook, usesPhysRegsForPEI, which is true for non-virtual targets. When it is true, all the phases operate as before, and PEI requires the AllVRegsAllocated property on MachineFunctions. Otherwise, CSR spilling and scavenging are skipped and only prolog/epilog insertion/frame finalization is done. Differential Revision: http://reviews.llvm.org/D18366 llvm-svn: 269750
* [WebAssembly] Move register stackification and coloring to a late phase.Dan Gohman2016-05-101-23/+27
| | | | | | | | | | | | | | | | | | | Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* Disable the PatchableFunction pass for NVPTX & WasmSanjoy Das2016-04-191-0/+1
| | | | | | | PatchableFunction requires AllVRegsAllocated that these targets don't provide. llvm-svn: 266720
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [WebAssembly] Remove duplicate disabling of passesDerek Schuff2016-03-281-12/+6
| | | | | | Also put all the disabled passes together llvm-svn: 264684
* Introduce MachineFunctionProperties and the AllVRegsAllocated propertyDerek Schuff2016-03-281-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | MachineFunctionProperties represents a set of properties that a MachineFunction can have at particular points in time. Existing examples of this idea are MachineRegisterInfo::isSSA() and MachineRegisterInfo::tracksLiveness() which will eventually be switched to use this mechanism. This change introduces the AllVRegsAllocated property; i.e. the property that all virtual registers have been allocated and there are no VReg operands left. With this mechanism, passes can declare that they require a particular property to be set, or that they set or clear properties by implementing e.g. MachineFunctionPass::getRequiredProperties(). The MachineFunctionPass base class verifies that the requirements are met, and handles the setting and clearing based on the delcarations. Passes can also directly query and update the current properties of the MF if they want to have conditional behavior. This change annotates the target-independent post-regalloc passes; future changes will also annotate target-specific ones. Reviewers: qcolombet, hfinkel Differential Revision: http://reviews.llvm.org/D18421 llvm-svn: 264593
* [WebAssembly] Implement irreducible control flow.Dan Gohman2016-03-091-0/+3
| | | | | | | | This implements a very simple conservative transformation that doesn't require more than linear code size growth. There's room for much more optimization in this space. llvm-svn: 262982
* [WebAssembly] Re-enable the TailDuplicate pass.Dan Gohman2016-02-221-1/+0
| | | | llvm-svn: 261566
* [WebAssembly] Don't use setRequiresStructuredCFG(true).Dan Gohman2016-02-181-3/+4
| | | | | | | | | | | | While we still do want reducible control flow, the RequiresStructuredCFG flag imposes more strict structure constraints than WebAssembly wants. Unsetting this flag enables critical edge splitting and tail merging. Also, disable TailDuplication explicitly, as it doesn't support virtual registers, and was previously only disabled by the RequiresStructuredCFG flag. llvm-svn: 261190
* [WebAssembly] Disable register stackification and coloring when not optimizingDerek Schuff2016-02-171-4/+6
| | | | | | | | | | | | | | These passes are optimizations, and should be disabled when not optimizing. Also create an MCCodeGenInfo so the opt level is correctly plumbed to the backend pass manager. Also remove the command line flag for disabling register coloring; running llc with -O0 should now be useful for debugging, so it's not necessary. Differential Revision: http://reviews.llvm.org/D17327 llvm-svn: 261176
* [WebAssembly] Implement unaligned loads and stores.Dan Gohman2016-01-261-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
* [WebAssembly] Disable some WebAssembly-specific optimization passes at -O0.Dan Gohman2016-01-191-3/+6
| | | | llvm-svn: 258127
* [WebAssembly] Add -m:e to the target triple.Dan Gohman2016-01-071-2/+3
| | | | | | | This enables ELF-style name mangling, which primarily means using ".L" for private symbols. llvm-svn: 257020
* [WebAssembly] Fix handling of COPY instructions in WebAssemblyRegStackify.Dan Gohman2015-12-251-6/+3
| | | | | | | | | | | | | Move RegStackify after coalescing and teach it to use LiveIntervals instead of depending on SSA form. This avoids a problem where a register in a COPY instruction is stackified and then subsequently coalesced with a register that is not stackified. This also puts it after the scheduler, which allows us to simplify the EXPR_STACK constraint, as we no longer have instructions being reordered after stackification and before coloring. llvm-svn: 256402
* [WebAssembly] Convert WebAssemblyTargetObjectFile to TargetLoweringObjectFileELFDan Gohman2015-12-171-2/+2
| | | | llvm-svn: 255877
* [WebAssembly] Experimental ELF writer supportDan Gohman2015-12-171-4/+3
| | | | | | | | | This creates the initial infrastructure for writing ELF output files. It doesn't yet have any implementation for encoding instructions. Differential Revision: http://reviews.llvm.org/D15555 llvm-svn: 255869
* [WebAssembly] Implement eliminateCallFramePseudoDerek Schuff2015-12-161-0/+3
| | | | | | | | | | | | | | | | | | Summary: Implement eliminateCallFramePsuedo to handle ADJCALLSTACKUP/DOWN pseudo-instructions. Add a test calling a vararg function which causes non-0 adjustments. This revealed an issue with RegisterCoalescer wherein it eliminates a COPY from SP32 to a vreg but failes to update the live ranges of EXPR_STACK, causing a machineinstr verifier failure (so this test is commented out). Also add a dynamic alloca test, which causes a callseq_end dag node with a 0 (instead of undef) second argument to be generated. We currently fail to select that, so adjust the ADJCALLSTACKUP tablegen code to handle it. Differential Revision: http://reviews.llvm.org/D15587 llvm-svn: 255844
* [WebAssembly] Implement prolog/epilog insertion and FrameIndex eliminationDerek Schuff2015-12-111-1/+7
| | | | | | | | | | | | | | | | | | Summary: Use the SP32 physical register as the base for FrameIndex lowering. Update it and the __stack_pointer global var in the prolog and epilog. Extend the mapping of virtual registers to wasm locals to include the physical registers. Rather than modify the target-independent PrologEpilogInserter (which asserts that there are no virtual registers left) include a slightly-modified copy for Wasm that does not have this assertion and only clears the virtual registers if scavenging was needed (which of course it isn't for wasm). Differential Revision: http://reviews.llvm.org/D15344 llvm-svn: 255392
* [WebAssembly] Reintroduce ARGUMENT moving logicDan Gohman2015-12-091-0/+4
| | | | | | | | | | | | | | | | | | | Reinteroduce the code for moving ARGUMENTS back to the top of the basic block. While the ARGUMENTS physical register prevents sinking and scheduling from moving them, it does not appear to be sufficient to prevent SelectionDAG from moving them down in the initial schedule. This patch introduces a patch that moves them back to the top immediately after SelectionDAG runs. This is still hopefully a temporary solution. http://reviews.llvm.org/D14750 is one alternative, though the review has not been favorable, and proposed alternatives are longer-term and have other downsides. This fixes the main outstanding -verify-machineinstrs failures, so it adds -verify-machineinstrs to several tests. Differential Revision: http://reviews.llvm.org/D15377 llvm-svn: 255125
* [WebAssembly] Call TargetPassConfig base class functions in overriding ↵Dan Gohman2015-12-051-1/+11
| | | | | | functions. llvm-svn: 254855
* [WebAssembly] Implement ReverseBranchCondition, and re-enable ↵Dan Gohman2015-12-051-4/+3
| | | | | | | | | | | | | MachineBlockPlacement This patch introduces a codegen-only instruction currently named br_unless, which makes it convenient to implement ReverseBranchCondition and re-enable the MachineBlockPlacement pass. Then in a late pass, it lowers br_unless back into br_if. Differential Revision: http://reviews.llvm.org/D14995 llvm-svn: 254826
* [WebAssembly] Delete unused functions. NFC.Dan Gohman2015-11-291-6/+0
| | | | llvm-svn: 254268
* [WebAssembly] Minor clang-format and selected clang-tidy cleanups. NFC.Dan Gohman2015-11-291-3/+2
| | | | llvm-svn: 254267
* [WebAssembly] Add some comments. NFC.Dan Gohman2015-11-251-0/+5
| | | | llvm-svn: 254096
* [WebAssembly] Clean up several FIXME comments.Dan Gohman2015-11-251-4/+4
| | | | llvm-svn: 254079
* [WebAssembly] Support for register stackifying with load and store instructions.Dan Gohman2015-11-251-0/+7
| | | | llvm-svn: 254076
* [WebAssembly] Emit .param, .result, and .local through MC.Dan Gohman2015-11-231-0/+1
| | | | | | This eliminates one of the main remaining uses of EmitRawText. llvm-svn: 253878
* [WebAssembly] Enable register coloring and register stackifying.Dan Gohman2015-11-181-1/+7
| | | | | | | | | | | | | | | | This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
* [WebAssembly] Reapply r252858, with svn add for the new file.Dan Gohman2015-11-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | Switch to MC for instruction printing. This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing does not use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252910
* Revert r252858: "[WebAssembly] Switch to MC for instruction printing."Hans Wennborg2015-11-121-1/+0
| | | | | | | | It broke the CMake build: "Cannot find source file: WebAssemblyRegNumbering.cpp" llvm-svn: 252897
* [WebAssembly] Switch to MC for instruction printing.Dan Gohman2015-11-121-0/+1
| | | | | | | | | | | | | | | | | | | | This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252858
* [WebAssembly] Support 'unreachable' expressionDerek Schuff2015-11-101-0/+6
| | | | | | | | | | | | | | | Lower LLVM's 'unreachable' terminator to ISD::TRAP, and lower ISD::TRAP to wasm's 'unreachable' expression. WebAssembly type-checks expressions, but a noreturn function with a return type that doesn't match the context will cause a check failure. So we lower LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 'unreachable' expression, which typechecks in any context and causes a trap if executed. Differential Revision: http://reviews.llvm.org/D14515 llvm-svn: 252566
* Try to fix WebAssembly build after r247864Hans Wennborg2015-09-161-1/+1
| | | | llvm-svn: 247870
* [WebAssembly] Check in an initial CFG Stackifier passDan Gohman2015-09-161-1/+7
| | | | | | | | | | | | This pass implements a simple algorithm for conversion from CFG to wasm's structured control flow. It doesn't yet handle multiple-entry loops; that will be added in a future patch. It also adds initial support for switch statements. Differential Revision: http://reviews.llvm.org/D12735 llvm-svn: 247818
* [WebAssembly] Support running without a register allocator in the default ↵Dan Gohman2015-09-081-35/+0
| | | | | | | | | | | | | CodeGen passes This allows backends which don't use a traditional register allocator, but do need PHI lowering and other passes, to use the default TargetPassConfig::addFastRegAlloc and TargetPassConfig::addOptimizedRegAlloc implementations. Differential Revision: http://reviews.llvm.org/D12691 llvm-svn: 247065
* [WebAssembly] Enable SSA lowering and other pre-regalloc passesDan Gohman2015-09-081-1/+21
| | | | llvm-svn: 247008
* [WebAssembly] Use the default alignment for SIMD types.Dan Gohman2015-08-191-2/+2
| | | | | | | | | Previously WebAssembly's datalayout string had -v128:8:128. This had been an attempt to declare a certain level of support for unaligned SIMD accesses. However, clang makes its own determinations for SIMD alignment that are independent of the datalayout string, so this wasn't actually meaningful. llvm-svn: 245494
* Use llvm::make_unique to fix the MSVC build.Rafael Espindola2015-08-111-1/+1
| | | | llvm-svn: 244641
* WebAssembly: print basic integer assembly.JF Bastien2015-07-311-1/+9
| | | | | | | | | | | | | | | | | | | Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
* WebAssembly: start instructionsJF Bastien2015-07-011-3/+9
| | | | | | | | | | | | | | | | | | | | Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
* [WebAssembly] Define separate Target instances for 32-bit and 64-bit.Dan Gohman2015-07-011-1/+2
| | | | llvm-svn: 241193
* [WebAssembly] Initial WebAssembly backendDan Gohman2015-06-291-0/+166
This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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