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* [WebAssembly] Remove unused memory instructions and patternsThomas Lively2019-09-231-51/+0
| | | | | | | | | | | | | | | | Summary: Removes duplicated SIMD loads and store instructions and removes patterns involving GlobalAddresses that were not used in any tests. Reviewers: aheejin, sunfish Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67783 llvm-svn: 372648
* [WebAssembly] Initial implementation of PIC code generationSam Clegg2019-03-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | This change implements lowering of references global symbols in PIC mode. This change implements lowering of global references in PIC mode using a new @GOT reference type. @GOT references can be used with function or data symbol names combined with the get_global instruction. In this case the linker will insert the wasm global that stores the address of the symbol (either in memory for data symbols or in the wasm table for function symbols). For now I'm continuing to use the R_WASM_GLOBAL_INDEX_LEB relocation type for this type of reference which means that this relocation type can refer to either a global or a function or data symbol. We could choose to introduce specific relocation types for GOT entries in the future. See the current dynamic linking proposal: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Differential Revision: https://reviews.llvm.org/D54647 llvm-svn: 357022
* [WebAssembly] Remove unused load/store patterns that use texternalsymSam Clegg2019-03-151-76/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D59395 llvm-svn: 356221
* [WebAssembly] Use named operands to identify loads and storesThomas Lively2019-03-091-2/+2
| | | | | | | | | | | | | | | | | | | Summary: Uses the named operands tablegen feature to look up the indices of offset, address, and p2align operands for all load and store instructions. This replaces brittle, incorrect logic for identifying loads and store when eliminating frame indices, which previously crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59007 llvm-svn: 355770
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [WebAssembly] Remove old intrinsicsDan Gohman2019-01-141-29/+0
| | | | | | | | | This removes the old grow_memory and mem.grow-style intrinsics, leaving just the memory.grow-style intrinsics. Differential Revision: https://reviews.llvm.org/D56645 llvm-svn: 351084
* [WebAssembly] Always use the version of computeKnownBits that returns a ↵Simon Pilgrim2018-12-211-4/+2
| | | | | | | | value. NFCI. Continues the work started by @bogner in rL340594 to remove uses of the KnownBits output paramater version. llvm-svn: 349911
* [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS] (fixed)Thomas Lively2018-10-111-22/+0
| | | | llvm-svn: 344287
* [WebAssembly] Revert rL344180, which was breaking expensive checksThomas Lively2018-10-111-0/+22
| | | | llvm-svn: 344280
* [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS]Thomas Lively2018-10-101-22/+0
| | | | | | | | | | | | | Summary: By moving that line into the `I` multiclass. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53093 llvm-svn: 344180
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-271-4/+6
| | | | | | | | | | | | | | | | | | | | | Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
* [WebAssembly] Fix typos in mem.grow/memory.grow opcodesHeejin Ahn2018-08-221-2/+2
| | | | | | This should be not 0x3f but 0x40. llvm-svn: 340373
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-08-131-6/+4
| | | | | | This reverts commit 917a99b71ce21c975be7bfbf66f4040f965d9f3c. llvm-svn: 339630
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-101-4/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: jfb, llvm-commits, aheejin, eraman, jgravelle-google, sbc100 Differential Revision: https://reviews.llvm.org/D50568 llvm-svn: 339474
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-07-271-6/+4
| | | | | | | This reverts commit d3c9af4179eae7793d1487d652e2d4e23844555f. (SVN revision 338164) llvm-svn: 338176
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-07-271-4/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D49160 llvm-svn: 338164
* [WebAssembly] Improve readability of load/stores and tests. NFC.Heejin Ahn2018-07-091-34/+31
| | | | | | | | | | | | | | | | | Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
* [WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.Wouter van Oortmerssen2018-06-181-70/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
* [WebAssembly] Update to the new names for the memory intrinsics.Dan Gohman2018-05-311-0/+9
| | | | | | | | | The WebAssembly committee has decided on the names `memory.size` and `memory.grow` for the memory intrinsics, so update the LLVM intrinsics to follow those names, keeping both sets of old names in place for compatibility. llvm-svn: 333708
* [WebAssembly] Fix the opcode number for i64.load16_u.Dan Gohman2018-05-171-1/+1
| | | | | | Fixes PR37488. llvm-svn: 332561
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [WebAssembly] Refactor tablegen for store instructions (NFC)Derek Schuff2018-03-301-194/+115
| | | | | | | | Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
* [WebAssembly] Add mem.* intrinsics.Dan Gohman2018-01-231-0/+9
| | | | | | | | | | | | The grow_memory and current_memory instructions are expected to be officially renamed to mem.grow and mem.size. Introduce new intrinsics with the new names. These new names aren't yet official, so for now, use them at your own risk. Also, take this opportunity to add arguments for the currently unused immediate field in those instructions. llvm-svn: 323222
* [WebAssembly] Add the rest of the atomic loadsDerek Schuff2017-10-051-48/+17
| | | | | | | | | | Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
* [WebAssembly] Refactor load ISel tablegen patterns into classesDerek Schuff2017-08-311-321/+208
| | | | | | | | | Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
* [WebAssembly] Fix use of SDNodeFlags after API change in r301803Derek Schuff2017-05-011-2/+2
| | | | llvm-svn: 301811
* [WebAssembly] Update calls to computeKnownBits after the changes from r301620.Craig Topper2017-04-281-5/+5
| | | | | | I didn't realize WebAssembly wasn't a default build target so I missed that changes were needed. llvm-svn: 301629
* [WebAssembly] Update grow_memory's return type.Dan Gohman2017-01-181-2/+2
| | | | | | | The grow_memory instruction now returns the previous memory size. Add the return type to the LLVM intrinsic. llvm-svn: 292322
* [WebAssembly] Annotate call and load/store immediates.Dan Gohman2016-12-231-23/+23
| | | | | | These will be used to guide the binary encoding of these immediates. llvm-svn: 290412
* [WebAssembly] Add immediate fields to call_indirect and memory operators.Dan Gohman2016-10-251-12/+9
| | | | | | | call_indirect, grow_memory, and current_memory now have immediate operands in the 0xd binary encoding. llvm-svn: 285085
* [WebAssembly] Reorder load/store operands to match binary encoding.Dan Gohman2016-10-251-284/+286
| | | | | | | The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
* [WebAssembly] Update opcode values according to recent spec changes.Dan Gohman2016-10-241-25/+25
| | | | | | This corresponds to the "0xd" opcode renumbering. llvm-svn: 285014
* [WebAssembly] Remove the output operand from stores.Dan Gohman2016-10-061-31/+27
| | | | | | | | | Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
* [WebAssembly] Add binary-encoding opcode values to instruction descriptions.Dan Gohman2016-10-051-25/+25
| | | | llvm-svn: 283389
* [WebAssembly] Disable folding of GA+reg into load/store constant offsetsDerek Schuff2016-08-311-6/+4
| | | | | | | | | | | Summary: If the register has a negative value then unsigned overflow will occur; this case is sometimes even created intentionally by LSR. For now disable GA+reg folding. Fixes PR29127 Differential Revision: https://reviews.llvm.org/D24053 llvm-svn: 280285
* [WebAssembly] Rename memory_size intrinsic to current_memoryDerek Schuff2016-05-021-9/+9
| | | | | | This follows the recent renaming in the wasm spec. llvm-svn: 268255
* [WebAssembly] Teach address folding to fold bitwise-or nodes.Dan Gohman2016-02-221-0/+68
| | | | | | | | | LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
* [WebAssembly] Implement unaligned loads and stores.Dan Gohman2016-01-261-242/+280
| | | | | | Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
* [WebAssembly] Reorganize address offset folding.Dan Gohman2016-01-111-85/+161
| | | | | | | | | | | | | Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
* [WebAssembly] Enclose the operand variables for load and store instructions ↵Dan Gohman2015-12-211-23/+23
| | | | | | | | | in braces. This allows the AsmMatcherEmitter to properly tokenize the AsmStrings for load and store instructions. This is a step towards asm parsing. llvm-svn: 256166
* [WebAssembly] Implement instruction selection for constant offsets in addresses.Dan Gohman2015-12-151-15/+360
| | | | | | | | | | | | | | | | | | | | Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
* [WebAssembly] Use an immediate OperandType for offset operands.Dan Gohman2015-12-151-23/+23
| | | | llvm-svn: 255612
* [WebAssembly] Support constant offsets on loads and storesDerek Schuff2015-12-051-74/+85
| | | | | | | | | This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
* [WebAssembly] Use a physical register to describe ARGUMENT liveness.Dan Gohman2015-11-251-0/+16
| | | | | | | | | | Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
* [WebAssembly] Clean up several FIXME comments.Dan Gohman2015-11-251-1/+1
| | | | llvm-svn: 254079
* [WebAssembly] Don't print the types of memory_size and grow_memoryDan Gohman2015-11-231-4/+4
| | | | | | This matches the current spec, for now. llvm-svn: 253931
* [WebAssembly] Model the return value of store instructions in wasm.Dan Gohman2015-11-231-27/+38
| | | | llvm-svn: 253916
* [WebAssembly] Use tabs instead of spaces in assembly output.Dan Gohman2015-11-151-27/+27
| | | | | | This seems to be the most popular convention among the other backends. llvm-svn: 253172
* [WebAssembly] Rename memory intrinsics to be upper-case, following ↵Dan Gohman2015-11-131-4/+4
| | | | | | convention. NFC. llvm-svn: 253070
* [WebAssembly] Fix copypasta.Dan Gohman2015-11-051-2/+2
| | | | | | Noticed by dschff in http://reviews.llvm.org/rL252203 llvm-svn: 252208
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