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* [WebAssembly] Update grow_memory's return type.Dan Gohman2017-01-181-2/+2
| | | | | | | The grow_memory instruction now returns the previous memory size. Add the return type to the LLVM intrinsic. llvm-svn: 292322
* [WebAssembly] Annotate call and load/store immediates.Dan Gohman2016-12-231-23/+23
| | | | | | These will be used to guide the binary encoding of these immediates. llvm-svn: 290412
* [WebAssembly] Add immediate fields to call_indirect and memory operators.Dan Gohman2016-10-251-12/+9
| | | | | | | call_indirect, grow_memory, and current_memory now have immediate operands in the 0xd binary encoding. llvm-svn: 285085
* [WebAssembly] Reorder load/store operands to match binary encoding.Dan Gohman2016-10-251-284/+286
| | | | | | | The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
* [WebAssembly] Update opcode values according to recent spec changes.Dan Gohman2016-10-241-25/+25
| | | | | | This corresponds to the "0xd" opcode renumbering. llvm-svn: 285014
* [WebAssembly] Remove the output operand from stores.Dan Gohman2016-10-061-31/+27
| | | | | | | | | Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
* [WebAssembly] Add binary-encoding opcode values to instruction descriptions.Dan Gohman2016-10-051-25/+25
| | | | llvm-svn: 283389
* [WebAssembly] Disable folding of GA+reg into load/store constant offsetsDerek Schuff2016-08-311-6/+4
| | | | | | | | | | | Summary: If the register has a negative value then unsigned overflow will occur; this case is sometimes even created intentionally by LSR. For now disable GA+reg folding. Fixes PR29127 Differential Revision: https://reviews.llvm.org/D24053 llvm-svn: 280285
* [WebAssembly] Rename memory_size intrinsic to current_memoryDerek Schuff2016-05-021-9/+9
| | | | | | This follows the recent renaming in the wasm spec. llvm-svn: 268255
* [WebAssembly] Teach address folding to fold bitwise-or nodes.Dan Gohman2016-02-221-0/+68
| | | | | | | | | LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
* [WebAssembly] Implement unaligned loads and stores.Dan Gohman2016-01-261-242/+280
| | | | | | Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
* [WebAssembly] Reorganize address offset folding.Dan Gohman2016-01-111-85/+161
| | | | | | | | | | | | | Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
* [WebAssembly] Enclose the operand variables for load and store instructions ↵Dan Gohman2015-12-211-23/+23
| | | | | | | | | in braces. This allows the AsmMatcherEmitter to properly tokenize the AsmStrings for load and store instructions. This is a step towards asm parsing. llvm-svn: 256166
* [WebAssembly] Implement instruction selection for constant offsets in addresses.Dan Gohman2015-12-151-15/+360
| | | | | | | | | | | | | | | | | | | | Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
* [WebAssembly] Use an immediate OperandType for offset operands.Dan Gohman2015-12-151-23/+23
| | | | llvm-svn: 255612
* [WebAssembly] Support constant offsets on loads and storesDerek Schuff2015-12-051-74/+85
| | | | | | | | | This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
* [WebAssembly] Use a physical register to describe ARGUMENT liveness.Dan Gohman2015-11-251-0/+16
| | | | | | | | | | Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
* [WebAssembly] Clean up several FIXME comments.Dan Gohman2015-11-251-1/+1
| | | | llvm-svn: 254079
* [WebAssembly] Don't print the types of memory_size and grow_memoryDan Gohman2015-11-231-4/+4
| | | | | | This matches the current spec, for now. llvm-svn: 253931
* [WebAssembly] Model the return value of store instructions in wasm.Dan Gohman2015-11-231-27/+38
| | | | llvm-svn: 253916
* [WebAssembly] Use tabs instead of spaces in assembly output.Dan Gohman2015-11-151-27/+27
| | | | | | This seems to be the most popular convention among the other backends. llvm-svn: 253172
* [WebAssembly] Rename memory intrinsics to be upper-case, following ↵Dan Gohman2015-11-131-4/+4
| | | | | | convention. NFC. llvm-svn: 253070
* [WebAssembly] Fix copypasta.Dan Gohman2015-11-051-2/+2
| | | | | | Noticed by dschff in http://reviews.llvm.org/rL252203 llvm-svn: 252208
* [WebAssembly] Add AsmString strings for most instructions.Dan Gohman2015-11-051-27/+54
| | | | | | | | | Mangling type information into MachineInstr opcode names was a temporary measure, and it's starting to get hairy. At the same time, the MC instruction printer wants to use AsmString strings for printing. This patch takes the first step, starting the process of adding AsmStrings for instructions. llvm-svn: 252203
* [WebAssembly] Update wasm builtin functions to match spec changes.Dan Gohman2015-11-051-15/+7
| | | | | | | The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252202
* WebAssembly: fix load/store syntaxJF Bastien2015-10-161-51/+51
| | | | | | | | | | | | Summary: The syntax has changed a bit recently. Reviewers: binji Subscribers: llvm-commits, jfb, sunfish, dschuff Differential Revision: http://reviews.llvm.org/D13821 llvm-svn: 250535
* [WebAssembly] Remove a TODO comment which is no longer needed. NFC.Dan Gohman2015-10-131-7/+0
| | | | llvm-svn: 250233
* [WebAssembly] Add a resize_memory intrinsic.Dan Gohman2015-10-021-0/+8
| | | | llvm-svn: 249178
* [WebAssembly] Add a memory_size intrinsic.Dan Gohman2015-10-021-0/+8
| | | | llvm-svn: 249171
* [WebAssembly] Rename several functions and types according to the new spec.Dan Gohman2015-09-261-55/+55
| | | | llvm-svn: 248644
* WebAssembly: generate load/storeJF Bastien2015-08-311-26/+73
| | | | | | | | | Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
* [WebAssembly] CodeGen support for __builtin_wasm_page_size()Dan Gohman2015-08-241-0/+7
| | | | llvm-svn: 245872
* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-101-0/+46
Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
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