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path: root/llvm/lib/Target/TargetSelectionDAG.td
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* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-898/+0
| | | | | | they can be distributed along with the header files. llvm-svn: 59953
* Added CONVERT_RNDSAT (conversion with rounding and saturation) SDNode toMon P Wang2008-11-101-0/+54
| | | | | | | support targets that support these conversions. Users should avoid using this node as the current targets don't generating code for it. llvm-svn: 59001
* Whitespace fixes. No functionality change.Bill Wendling2008-10-311-27/+27
| | | | llvm-svn: 58539
* Now that predicates can be composed, simplify several ofDan Gohman2008-10-151-173/+123
| | | | | | | | | | | | | the predicates by extending simple predicates to create more complex predicates instead of duplicating the logic for the simple predicates. This doesn't reduce much redundancy in DAGISelEmitter.cpp's generated source yet; that will require improvements to DAGISelEmitter.cpp's instruction sorting, to make it more effectively group nodes with similar predicates together. llvm-svn: 57565
* Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's asChris Lattner2008-10-111-0/+1
| | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. llvm-svn: 57385
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-161-4/+4
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-161-4/+4
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Split the ATOMIC NodeType's to include the size, e.g.Dale Johannesen2008-08-281-184/+84
| | | | | | | | | | | | | | | | ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD. Increased the Hardcoded Constant OpActionsCapacity to match. Large but boring; no functional change. This is to support partial-word atomics on ppc; i8 is not a valid type there, so by the time we get to lowering, the ATOMIC_LOAD nodes looks the same whether the type was i8 or i32. The information can be added to the AtomicSDNode, but that is the largest SDNode; I don't fully understand the SDNode allocation, but it is sensitive to the largest node size, so increasing that must be bad. This is the alternative. llvm-svn: 55457
* Implement 32 & 64 bit versions of PPC atomicDale Johannesen2008-08-251-0/+105
| | | | | | binary primitives. llvm-svn: 55343
* Add libm-oriented ISD opcodes for rounding operations.Dan Gohman2008-08-211-0/+5
| | | | llvm-svn: 55130
* Clean up a dead return missed in r55055.Dan Gohman2008-08-201-3/+2
| | | | llvm-svn: 55057
* Tablegen generated code already tests the opcode value, so it's notDan Gohman2008-08-201-204/+148
| | | | | | necessary to use dyn_cast in these predicates. llvm-svn: 55055
* Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.Bill Wendling2008-08-201-28/+3
| | | | | | Just expand it like the other X-bit sub_and_fetches. llvm-svn: 55023
* Add support for the __sync_sub_and_fetch atomics and friends for X86. The codeBill Wendling2008-08-191-3/+28
| | | | | | was already present, but not hooked up to anything. llvm-svn: 55018
* Since build_vector is a variadic node, the numberDuncan Sands2008-07-281-1/+1
| | | | | | of operands should be -1 not 0. llvm-svn: 54141
* Remove the OrigVT member from AtomicSDNode, as it is redundant withDan Gohman2008-06-251-12/+12
| | | | | | the base SDNode's VTList. llvm-svn: 52722
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-35/+36
| | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub llvm-svn: 52706
* add missing atomic intrinsic from gccAndrew Lenharth2008-06-141-0/+2
| | | | llvm-svn: 52270
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-4/+4
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-311-2/+1
| | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. llvm-svn: 51808
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-0/+1
| | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
* Add support for vicmp/vfcmp codegen, more legalize support coming.Nate Begeman2008-05-121-0/+1
| | | | | | This is necessary to unbreak the build. llvm-svn: 50988
* Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang2008-05-051-0/+16
| | | | llvm-svn: 50663
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-8/+0
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-131-1/+6
| | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. llvm-svn: 48329
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-7/+16
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Atomic op support. If any gcc test uses __sync builtins, it might start ↵Andrew Lenharth2008-02-211-0/+91
| | | | | | failing on archs that haven't implemented them yet llvm-svn: 47430
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-161-0/+7
| | | | llvm-svn: 47204
* Change how FP immediates are handled. Nate Begeman2008-02-141-2/+1
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Enable SSE4 codegen and pattern matching.Nate Begeman2008-02-111-2/+2
| | | | | | Add some notes to the README. llvm-svn: 46949
* Tablegen support for insert & extract element matchingNate Begeman2008-02-091-0/+16
| | | | llvm-svn: 46901
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb2008-01-311-1/+9
| | | | | | | | | | complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. llvm-svn: 46606
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-29/+29
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* This commit changes:Chris Lattner2008-01-171-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-2/+4
| | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. llvm-svn: 46017
* add SDNPSideEffect node property declarationChris Lattner2008-01-101-0/+1
| | | | llvm-svn: 45825
* add SDNPMayLoad to the 'load' sdnode definition. This is enough to get all ↵Chris Lattner2008-01-101-1/+3
| | | | | | | | the x86 instructions (with patterns) that load memory marked, for example. llvm-svn: 45818
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-2/+5
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* add a immAllZerosV_bc pattern fragment for consistency with others.Chris Lattner2007-11-241-3/+6
| | | | llvm-svn: 44303
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-0/+5
| | | | llvm-svn: 44045
* Rename keyword "modify" -> "implicit".Evan Cheng2007-09-251-1/+1
| | | | llvm-svn: 42282
* Initial support for multi-result patterns:Evan Cheng2007-09-121-0/+2
| | | | | | | | | | | | 1. [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), (modify EFLAGS)] This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS. 2. def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()> Similar to #1 except this is used for def : Pat patterns. llvm-svn: 41897
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-051-0/+14
| | | | | | Lots of problems yet but some simple things work. llvm-svn: 40847
* Add selection DAG nodes for subreg insert/extract. PR1350Christopher Lamb2007-07-261-0/+5
| | | | llvm-svn: 40516
* Fix comments about vectors to use the current wording.Dan Gohman2007-07-161-1/+1
| | | | llvm-svn: 39921
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-0/+4
| | | | | | X86 32 bits. llvm-svn: 36283
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-3/+0
| | | | llvm-svn: 33537
* Fix predicates for unindexed stores so they don't accidentally match indexedChris Lattner2006-11-141-33/+39
| | | | | | stores. llvm-svn: 31735
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