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path: root/llvm/lib/Target/TargetSelectionDAG.td
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* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-12/+12
| | | | llvm-svn: 31596
* Added indexed store node and patfrag's.Evan Cheng2006-11-081-11/+131
| | | | llvm-svn: 31576
* Change load PatFrag to ignore indexed load.Evan Cheng2006-10-261-31/+62
| | | | llvm-svn: 31210
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-12/+40
| | | | llvm-svn: 30945
* Add properties to ComplexPattern.Evan Cheng2006-10-111-1/+3
| | | | llvm-svn: 30891
* Naming consistency.Evan Cheng2006-10-111-13/+13
| | | | llvm-svn: 30878
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-16/+74
| | | | llvm-svn: 30844
* Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng2006-10-041-12/+10
| | | | | | extra operand to LOADX to specify the exact value extension type. llvm-svn: 30714
* Vector extract / insert index operand should have ptr type.Evan Cheng2006-06-151-2/+2
| | | | llvm-svn: 28798
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-0/+9
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* Renamed AddedCost to AddedComplexity.Evan Cheng2006-04-191-4/+4
| | | | llvm-svn: 27843
* Allow "let AddedCost = n in" to increase pattern complexity.Evan Cheng2006-04-191-1/+2
| | | | llvm-svn: 27834
* Add a new vnot_conv predicate for matching vnot's where the allones vector isChris Lattner2006-04-151-0/+6
| | | | | | bitconverted from some other type. llvm-svn: 27724
* Add vector_extract and vector_insert nodes.Evan Cheng2006-03-311-0/+4
| | | | llvm-svn: 27303
* Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum ↵Chris Lattner2006-03-281-3/+3
| | | | | | value. Split them into separate enums. llvm-svn: 27201
* Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.Evan Cheng2006-03-271-1/+1
| | | | llvm-svn: 27166
* Add immAllZerosV helperEvan Cheng2006-03-261-0/+3
| | | | llvm-svn: 27148
* add a vnot helper node for matching 'not' on vectorsChris Lattner2006-03-251-2/+6
| | | | llvm-svn: 27132
* Add new intrinsic node definitions for tblgen useChris Lattner2006-03-251-0/+12
| | | | llvm-svn: 27100
* Shuffle some includes aroundChris Lattner2006-03-241-3/+0
| | | | llvm-svn: 27073
* expose intrinsic info to the targets.Chris Lattner2006-03-241-0/+3
| | | | llvm-svn: 27070
* x86 ISD::SCALAR_TO_VECTOR support.Evan Cheng2006-03-211-0/+2
| | | | llvm-svn: 26911
* Add a build_vector nodeChris Lattner2006-03-201-1/+1
| | | | llvm-svn: 26895
* add vector_shuffleChris Lattner2006-03-201-0/+16
| | | | llvm-svn: 26891
* add support for the bitconvert nodeChris Lattner2006-03-161-0/+3
| | | | llvm-svn: 26789
* relax fcopysignAndrew Lenharth2006-03-091-1/+4
| | | | llvm-svn: 26649
* fcopysign supportAndrew Lenharth2006-03-091-0/+1
| | | | llvm-svn: 26640
* remove the read/write port/io intrinsics.Chris Lattner2006-03-031-11/+0
| | | | llvm-svn: 26479
* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-171-1/+8
| | | | | | | and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. llvm-svn: 26255
* Whoops, didn't mean to check this in yet.Nate Begeman2006-02-171-8/+0
| | | | llvm-svn: 26250
* Add a missing and useful pat fragNate Begeman2006-02-171-2/+9
| | | | llvm-svn: 26249
* Targets all now request ConstantFP to be legalized into TargetConstantFP.Chris Lattner2006-01-291-1/+2
| | | | | | 'fpimm' in .td files is now TargetConstantFP. llvm-svn: 25771
* bswap implementationNate Begeman2006-01-141-0/+1
| | | | llvm-svn: 25312
* Add bswap, rotl, and rotr nodesNate Begeman2006-01-111-0/+2
| | | | | | | | | Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them llvm-svn: 25222
* New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replaceEvan Cheng2006-01-091-0/+3
| | | | | | hasInFlag, hasOutFlag. llvm-svn: 25155
* Added fpimm node for ConstantFP.Evan Cheng2006-01-051-0/+2
| | | | llvm-svn: 25107
* Added initial support for DEBUG_LABEL allowing debug specific labels to beJim Laskey2006-01-051-3/+6
| | | | | | inserted in the code. llvm-svn: 25104
* Add unique id to debug location for debug label use (work in progress.)Jim Laskey2006-01-041-2/+2
| | | | llvm-svn: 25096
* Add support for brcondAndrew Lenharth2006-01-011-0/+5
| | | | llvm-svn: 25058
* support targetexternalsymAndrew Lenharth2005-12-241-13/+16
| | | | llvm-svn: 25005
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-1/+0
| | | | | | | | * Added a pseudo instruction (for each target) that represent "return void". This is a workaround for lack of optional flag operand (return void is not lowered so it does not have a flag operand.) llvm-svn: 24997
* Operand 1 of TRUNCSTORE can be any of integer and floating point types.Evan Cheng2005-12-231-1/+1
| | | | llvm-svn: 24989
* Added special flag node FLAG.Evan Cheng2005-12-221-0/+1
| | | | llvm-svn: 24934
* add some nodes, forgot to commit this last night :(Chris Lattner2005-12-211-0/+2
| | | | llvm-svn: 24901
* Added X86 readport patterns.Evan Cheng2005-12-201-0/+5
| | | | llvm-svn: 24879
* X86 conditional branch support.Evan Cheng2005-12-191-5/+0
| | | | llvm-svn: 24870
* add a node, for completenessChris Lattner2005-12-181-0/+2
| | | | llvm-svn: 24819
* Since extload can also be used by FP, split STDIntExtLoad into two parts,Nate Begeman2005-12-181-2/+5
| | | | | | | one for use with extload, one for use with sextload and zextload, which are integer only. llvm-svn: 24814
* add truncstoreChris Lattner2005-12-171-3/+9
| | | | llvm-svn: 24787
* Added source file/line correspondence for dwarf (PowerPC only at this point.)Jim Laskey2005-12-161-0/+10
| | | | llvm-svn: 24748
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