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* Fix Target->Codegen dependence.Andrew Trick2012-06-081-195/+5
| | | | | | | | | | | | | | | | | Bulk move of TargetInstrInfo implementation into TargetInstrInfoImpl. This is dirty because the code isn't part of TargetInstrInfoImpl class, nor should it be, because the methods are not target hooks. However, it's the current mechanism for keeping libTarget useful outside the backend. You'll get a not-so-nice link error if you invoke a TargetInstrInfo method that depends on CodeGen. The TargetInstrInfoImpl class should probably be removed since it doesn't really solve this problem. To really fix this, we probably need separate interfaces for the CodeGen/nonCodeGen sides of TargetInstrInfo. llvm-svn: 158212
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-23/+65
| | | | llvm-svn: 158164
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-9/+112
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+3
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Move parts of lib/Target that use CodeGen into lib/CodeGen.Nick Lewycky2011-12-151-29/+0
| | | | llvm-svn: 146702
* Move isUnpredicatedTerminator() default implementation to ↵Evan Cheng2011-12-091-12/+0
| | | | | | TargetInstrInfoImpl to break Target's dependency on CodeGen. llvm-svn: 146247
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+3
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-7/+0
| | | | llvm-svn: 134244
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-1/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+4
| | | | llvm-svn: 134030
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-11/+10
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-18/+18
| | | | llvm-svn: 133944
* Clean up assembly statement separator support.Jim Grosbach2011-03-241-3/+4
| | | | | | | | The MC asm lexer wasn't honoring a non-default (anything but ';') statement separator. Fix that, and generalize a bit to support multi-character statement separators. llvm-svn: 128227
* whitespaceAndrew Trick2010-12-241-5/+5
| | | | llvm-svn: 122539
* Add missing standard headers. Patch by Joerg Sonnenberger!Nick Lewycky2010-12-191-0/+1
| | | | llvm-svn: 122193
* Add missing std:: prefixes to some calls. C++ doesn't require that <cfoo>Nick Lewycky2010-12-191-1/+1
| | | | | | | headers provide symbols outside namespace std and the LLVM coding standards state that we should prefix all of them. llvm-svn: 122192
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-2/+22
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-261-0/+10
| | | | llvm-svn: 117348
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-1/+32
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* Spelling fix.Bob Wilson2010-09-151-1/+1
| | | | llvm-svn: 113978
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-3/+3
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-091-0/+17
| | | | | | | | | | instruction in the class would be decoded to. Or zero if the number of uOPs must be determined dynamically. This will be used to determine the cost-effectiveness of predicating a micro-coded instruction. llvm-svn: 113513
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-0/+4
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* rename TAI -> MAI, being careful not to make MAILJMP instructions :)Chris Lattner2009-08-221-5/+5
| | | | llvm-svn: 79777
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-2/+2
| | | | llvm-svn: 79763
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-9/+48
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* move a virtual method body to its .cpp file to avoid a #include Chris Lattner2009-08-021-2/+9
| | | | | | in a header. llvm-svn: 77874
* inline the global 'getInstrOperandRegClass' function into its callersChris Lattner2009-07-291-10/+0
| | | | | | now that TargetOperandInfo does the heavy lifting. llvm-svn: 77508
* 1. Introduce a new TargetOperandInfo::getRegClass() helper methodChris Lattner2009-07-291-4/+13
| | | | | | | | | | | | | and convert code to using it, instead of having lots of things poke the isLookupPtrRegClass() method directly. 2. Make PointerLikeRegClass contain a 'kind' int, and store it in the existing regclass field of TargetOperandInfo when the isLookupPtrRegClass() predicate is set. Make getRegClass pass this into TargetRegisterInfo::getPointerRegClass(), allowing targets to have multiple ptr_rc things. llvm-svn: 77504
* Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.Evan Cheng2009-05-051-0/+13
| | | | llvm-svn: 70950
* Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson2009-04-091-13/+0
| | | | | | | | | | | | register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). llvm-svn: 68714
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-7/+7
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45680
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-10/+9
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-42/+0
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-4/+4
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* More cleanups for MachineOperand:Chris Lattner2007-12-301-8/+2
| | | | | | | | | | - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h llvm-svn: 45461
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-1/+1
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman2007-09-141-3/+3
| | | | | | | isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. llvm-svn: 41958
* isUnpredicatedTerminator should treat conditional branches as unpredicated ↵Evan Cheng2007-07-061-1/+4
| | | | | | terminator. llvm-svn: 37960
* Do not check isPredicated() on non-predicable instructions.Evan Cheng2007-07-051-1/+4
| | | | llvm-svn: 37891
* Add a utility routine to check for unpredicated terminator instruction.Evan Cheng2007-06-081-0/+7
| | | | llvm-svn: 37528
* Add missing const qualifiers.Evan Cheng2007-05-291-1/+1
| | | | llvm-svn: 37341
* Rename a parameter.Evan Cheng2007-05-231-4/+4
| | | | llvm-svn: 37307
* Remove. Not needed.Evan Cheng2007-05-171-4/+0
| | | | llvm-svn: 37139
* Default implementation of TargetInstrInfo::getBlockSize().Evan Cheng2007-05-161-0/+4
| | | | llvm-svn: 37138
* PredicateInstruction returns true if the operation was successful.Evan Cheng2007-05-161-14/+19
| | | | llvm-svn: 37124
* Add default implementation of PredicateInstruction().Evan Cheng2007-05-161-0/+20
| | | | llvm-svn: 37123
* Move findTiedToSrcOperand to TargetInstrDescriptor.Evan Cheng2006-12-081-12/+11
| | | | llvm-svn: 32366
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