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author | Evan Cheng <evan.cheng@apple.com> | 2011-06-28 19:10:37 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-28 19:10:37 +0000 |
commit | 6cc775f905a850905f9f437d1f67b99ab3f821b1 (patch) | |
tree | 9c4c91de40be70e7aa57d1b7702507d3328795b2 /llvm/lib/Target/TargetInstrInfo.cpp | |
parent | 6f306a48592be29c0fdaff98cd9c47c3e6eb343e (diff) | |
download | bcm5719-llvm-6cc775f905a850905f9f437d1f67b99ab3f821b1.tar.gz bcm5719-llvm-6cc775f905a850905f9f437d1f67b99ab3f821b1.zip |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
Diffstat (limited to 'llvm/lib/Target/TargetInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/TargetInstrInfo.cpp | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/llvm/lib/Target/TargetInstrInfo.cpp b/llvm/lib/Target/TargetInstrInfo.cpp index 2cb89f44401..66f8f607233 100644 --- a/llvm/lib/Target/TargetInstrInfo.cpp +++ b/llvm/lib/Target/TargetInstrInfo.cpp @@ -24,22 +24,21 @@ using namespace llvm; // TargetInstrInfo //===----------------------------------------------------------------------===// -TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc, - unsigned numOpcodes) - : Descriptors(Desc), NumOpcodes(numOpcodes) { +TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes) { + InitMCInstrInfo(Desc, numOpcodes); } TargetInstrInfo::~TargetInstrInfo() { } const TargetRegisterClass* -TargetInstrInfo::getRegClass(const TargetInstrDesc &TID, unsigned OpNum, +TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI) const { - if (OpNum >= TID.getNumOperands()) + if (OpNum >= MCID.getNumOperands()) return 0; - short RegClass = TID.OpInfo[OpNum].RegClass; - if (TID.OpInfo[OpNum].isLookupPtrRegClass()) + short RegClass = MCID.OpInfo[OpNum].RegClass; + if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) return TRI->getPointerRegClass(RegClass); // Instructions like INSERT_SUBREG do not have fixed register classes. @@ -135,13 +134,13 @@ void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isTerminator()) return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isTerminator()) return false; // Conditional branch is a special case. - if (TID.isBranch() && !TID.isBarrier()) + if (MCID.isBranch() && !MCID.isBarrier()) return true; - if (!TID.isPredicable()) + if (!MCID.isPredicable()) return true; return !isPredicated(MI); } |