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* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-499/+0
| | | | | | they can be distributed along with the header files. llvm-svn: 59953
* Mark IMPLICIT_DEF as being rematerializable and cheap-as-a-move.Dan Gohman2008-09-091-0/+2
| | | | | | | | It's already special-cased and treated as rematerializable within LiveIntervals; this allows it to be handled by other passes such as TwoAddressInstrctionPass. llvm-svn: 55999
* TargetRegisterDesc::Name field is the same as the abstract register name. ↵Evan Cheng2008-07-071-1/+0
| | | | | | There is no need for targets to specify register names in addition to their AsmName's. llvm-svn: 53207
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-2/+16
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-311-6/+0
| | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. llvm-svn: 51808
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-0/+6
| | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-281-1/+4
| | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. llvm-svn: 51660
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-0/+8
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
| | | | llvm-svn: 48381
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-0/+7
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-4/+8
| | | | | | failures. llvm-svn: 48223
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-8/+4
| | | | llvm-svn: 48167
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-4/+8
| | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. llvm-svn: 48130
* Rename PrintableName to Name.Bill Wendling2008-02-261-1/+1
| | | | llvm-svn: 47629
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-1/+1
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling2008-02-241-0/+1
| | | | | | | | | %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. llvm-svn: 47534
* Move some useful operands up into the all-targets .tdNate Begeman2008-02-141-0/+3
| | | | llvm-svn: 47115
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-1/+8
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-1/+1
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-6/+9
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* add a new bit.Chris Lattner2008-01-071-1/+2
| | | | llvm-svn: 45726
* remove a dead field.Chris Lattner2008-01-071-1/+0
| | | | llvm-svn: 45685
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* As per feedback, revised comments to (hopefully) make the different side effectBill Wendling2007-12-171-3/+12
| | | | | | flags clearer. llvm-svn: 45120
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-0/+5
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-0/+1
| | | | | | re-materializable and they should not be spilled. llvm-svn: 44960
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* Clarify the meaning of '-2' register numberAnton Korobeynikov2007-11-111-2/+4
| | | | llvm-svn: 43998
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-5/+5
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+6
| | | | | | between two registers in the specific class. llvm-svn: 42123
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-7/+0
| | | | llvm-svn: 41863
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-0/+12
| | | | | | MBB's. PR1350 llvm-svn: 40518
* No more noResults.Evan Cheng2007-07-211-1/+0
| | | | llvm-svn: 40132
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-6/+14
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Remove clobbersPred.Evan Cheng2007-07-101-1/+0
| | | | llvm-svn: 38500
* Do away with ImmutablePredicateOperand.Evan Cheng2007-07-061-8/+1
| | | | llvm-svn: 37959
* Add OptionalDefOperand to stand for optionally defined result.Evan Cheng2007-07-061-7/+10
| | | | llvm-svn: 37930
* - Added zero_reg def to stand for register 0.Evan Cheng2007-07-051-2/+19
| | | | | | - Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand. llvm-svn: 37892
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add support to tablegen for specifying subregister classes on a per register ↵Christopher Lamb2007-06-131-0/+4
| | | | | | class basis. llvm-svn: 37572
* Added clobbersPred.Evan Cheng2007-06-061-0/+1
| | | | llvm-svn: 37466
* Added isPredicable bit to class Instruction.Evan Cheng2007-05-161-0/+1
| | | | llvm-svn: 37117
* PredicateOperand can be used as a normal operand for isel.Evan Cheng2007-05-081-1/+1
| | | | llvm-svn: 36947
* Add an "implies" field to features. This indicates that, if the currentBill Wendling2007-05-041-1/+7
| | | | | | | | feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. llvm-svn: 36756
* expose HonorSignDependentRoundingFPMathOption to .td filesChris Lattner2007-05-031-0/+5
| | | | llvm-svn: 36658
* llvm bug #1350, parts 1, 2, and 3.Nate Begeman2007-05-011-7/+9
| | | | llvm-svn: 36618
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