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* Remove the .cvsignore file so this directory can be pruned.Reid Spencer2006-04-131-1/+0
| | | | llvm-svn: 27683
* Remove the SparcV8 backend. It has been renamed to be the Sparc backend.Chris Lattner2006-02-0519-3687/+0
| | | | llvm-svn: 25992
* Custom lower VAARG for the case when we are doing vaarg(double). In thisChris Lattner2006-02-041-3/+35
| | | | | | | case, the double being loaded may not be 8-byte aligned, so we have to use our standard bit_convert game. llvm-svn: 25967
* Fix a nasty typo that broke functions with big stack frames.Chris Lattner2006-02-041-1/+1
| | | | llvm-svn: 25966
* fix a bug in my last checkinChris Lattner2006-02-041-2/+2
| | | | llvm-svn: 25965
* add a noteChris Lattner2006-02-041-0/+1
| | | | llvm-svn: 25962
* Two changes:Chris Lattner2006-02-045-17/+24
| | | | | | | | | | 1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode 2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end up with commented out copies! This should fix a bunch of failures in V9 mode on sparc. llvm-svn: 25961
* Teach sparc to fold loads/stores into copies.Chris Lattner2006-02-032-37/+47
| | | | | | | Remove the dead getRegClassForType method minor formating changes. llvm-svn: 25936
* Implement isLoadFromStackSlot and isStoreToStackSlotChris Lattner2006-02-032-0/+52
| | | | llvm-svn: 25932
* %fcc is not an alias for %fcc0Chris Lattner2006-02-021-4/+4
| | | | llvm-svn: 25906
* correct an opcodeChris Lattner2006-02-021-2/+2
| | | | llvm-svn: 25905
* Allow the specification of explicit alignments for constant pool entries.Evan Cheng2006-01-311-1/+2
| | | | llvm-svn: 25855
* add a missing break that caused a lot of failures last night :(Chris Lattner2006-01-311-0/+1
| | | | llvm-svn: 25851
* okay, one moreChris Lattner2006-01-311-0/+2
| | | | llvm-svn: 25847
* another noteChris Lattner2006-01-311-1/+2
| | | | llvm-svn: 25846
* More notesChris Lattner2006-01-311-1/+15
| | | | llvm-svn: 25845
* another oneChris Lattner2006-01-311-0/+1
| | | | llvm-svn: 25844
* add a noteChris Lattner2006-01-311-0/+29
| | | | llvm-svn: 25843
* add conditional moves of float and double values on int/fp condition codes.Chris Lattner2006-01-311-6/+27
| | | | llvm-svn: 25842
* treat conditional branches the same way as conditional moves (giving themChris Lattner2006-01-313-129/+17
| | | | | | an operand that contains the condcode), making things significantly simpler. llvm-svn: 25840
* compactify all of the integer conditional moves into one instruction that takesChris Lattner2006-01-314-166/+144
| | | | | | a CC as an operand. Much smaller, much happier. llvm-svn: 25839
* Add immediate forms of integer cmovsChris Lattner2006-01-311-6/+49
| | | | llvm-svn: 25838
* ShrinkifyChris Lattner2006-01-311-143/+86
| | | | llvm-svn: 25837
* Add the full complement of conditional moves of integer registers.Chris Lattner2006-01-311-7/+115
| | | | llvm-svn: 25834
* Compile this:Chris Lattner2006-01-311-21/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | void %X(int %A) { %C = setlt int %A, 123 ; <bool> [#uses=1] br bool %C, label %T, label %F T: ; preds = %0 call int %main( int 0 ) ; <int>:0 [#uses=0] ret void F: ; preds = %0 ret void } to this: X: save -96, %o6, %o6 subcc %i0, 122, %l0 bg .LBBX_2 ! F nop ... not this: X: save -96, %o6, %o6 sethi 0, %l0 or %g0, 1, %l1 subcc %i0, 122, %l2 bg .LBBX_4 ! nop .LBBX_3: ! or %g0, %l0, %l1 .LBBX_4: ! subcc %l1, 0, %l0 bne .LBBX_2 ! F nop llvm-svn: 25833
* I don't see why this optimization isn't safe, but it isn't, so disable itChris Lattner2006-01-311-1/+2
| | | | llvm-svn: 25829
* Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure ↵Chris Lattner2006-01-301-0/+3
| | | | | | from last night llvm-svn: 25819
* Revamp the ICC/FCC reading instructions to be parameterized in terms of theChris Lattner2006-01-302-71/+212
| | | | | | | SPARC condition codes, not in terms of the DAG condcodes. This allows us to write nice clean patterns for cmovs/branches. llvm-svn: 25815
* Compile:Chris Lattner2006-01-302-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | uint %test(uint %X) { %Y = call uint %llvm.ctpop.i32(uint %X) ret uint %Y } to: test: save -96, %o6, %o6 sll %i0, 0, %l0 popc %l0, %i0 restore %g0, %g0, %g0 retl nop instead of to 40 logical ops. Note the shift-by-zero that clears the top part of the 64-bit V9 register. Testcase here: CodeGen/SparcV8/ctpop.ll llvm-svn: 25814
* If the target has V9 instructions, this pass is a noop, don't botherChris Lattner2006-01-301-8/+16
| | | | | | running it. llvm-svn: 25811
* When in v9 mode, emit fabsd/fnegd/fmovdChris Lattner2006-01-301-8/+30
| | | | llvm-svn: 25810
* First step towards V9 instructions in the V8 backend, two conditional moveChris Lattner2006-01-303-7/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patterns. This allows emission of this code: t1: save -96, %o6, %o6 subcc %i0, %i1, %l0 move %icc, %i0, %i2 or %g0, %i2, %i0 restore %g0, %g0, %g0 retl nop instead of this: t1: save -96, %o6, %o6 subcc %i0, %i1, %l0 be .LBBt1_2 ! nop .LBBt1_1: ! or %g0, %i2, %i0 .LBBt1_2: ! restore %g0, %g0, %g0 retl nop for this: int %t1(int %a, int %b, int %c) { %tmp.2 = seteq int %a, %b %tmp3 = select bool %tmp.2, int %a, int %c ret int %tmp3 } llvm-svn: 25809
* Two changes:Chris Lattner2006-01-301-0/+11
| | | | | | | 1. Default to having V9 instructions, instead of just V8. 2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta) llvm-svn: 25807
* When lowering SELECT_CC, see if the input is a lowered SETCC. If so, foldChris Lattner2006-01-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the two operations together. This allows us to compile this: void %two(int %a, int* %b) { %tmp.2 = seteq int %a, 0 %tmp.0.0 = select bool %tmp.2, int 10, int 20 store int %tmp.0.0, int* %b ret void } into: two: save -96, %o6, %o6 or %g0, 20, %l0 or %g0, 10, %l1 subcc %i0, 0, %l2 be .LBBtwo_2 ! entry nop .LBBtwo_1: ! entry or %g0, %l0, %l1 .LBBtwo_2: ! entry st %l1, [%i1] restore %g0, %g0, %g0 retl nop instead of: two: save -96, %o6, %o6 sethi 0, %l0 or %g0, 1, %l1 or %g0, 20, %l2 or %g0, 10, %l3 subcc %i0, 0, %l4 be .LBBtwo_2 ! entry nop .LBBtwo_1: ! entry or %g0, %l0, %l1 .LBBtwo_2: ! entry subcc %l1, 0, %l0 bne .LBBtwo_4 ! entry nop .LBBtwo_3: ! entry or %g0, %l2, %l3 .LBBtwo_4: ! entry st %l3, [%i1] restore %g0, %g0, %g0 retl nop llvm-svn: 25806
* Move MaskedValueIsZero from the DAGCombiner to the TargetLowering ↵Chris Lattner2006-01-301-6/+4
| | | | | | interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. llvm-svn: 25803
* Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,Chris Lattner2006-01-301-0/+26
| | | | | | allowing redundant and's to be eliminated by the dag combiner. llvm-svn: 25800
* Use V8ISD::CALL instead of ISD::CALLChris Lattner2006-01-272-5/+9
| | | | llvm-svn: 25716
* initialize member varsChris Lattner2006-01-271-0/+5
| | | | llvm-svn: 25712
* Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET forNate Begeman2006-01-271-29/+32
| | | | | | | the same functionality. This addresses another piece of bug 680. Next, on to fixing Alpha VAARG, which I broke last time. llvm-svn: 25696
* Subtarget feature can now set any variable to any valueEvan Cheng2006-01-271-3/+3
| | | | llvm-svn: 25678
* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-272-3/+0
| | | | llvm-svn: 25674
* Rest of subtarget support, remove references to ppcChris Lattner2006-01-264-14/+38
| | | | llvm-svn: 25642
* Add trivial subtarget supportChris Lattner2006-01-266-1/+86
| | | | llvm-svn: 25641
* Set SchedulingForLatency to be the default scheduling preference for all.Evan Cheng2006-01-251-1/+0
| | | | llvm-svn: 25607
* First part of bug 680:Nate Begeman2006-01-251-37/+18
| | | | | | | Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. llvm-svn: 25606
* Default scheduling preference is SchedulingForLatency.Evan Cheng2006-01-251-0/+1
| | | | llvm-svn: 25603
* remove the V8 simple iselChris Lattner2006-01-233-1840/+4
| | | | llvm-svn: 25534
* Add explicit #includes of <iostream>Chris Lattner2006-01-222-0/+2
| | | | llvm-svn: 25515
* Add explicit #includes of <iostream>Chris Lattner2006-01-221-0/+1
| | | | llvm-svn: 25509
* implement support for f32 arguments past the first 6 wordsChris Lattner2006-01-191-0/+5
| | | | llvm-svn: 25450
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