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* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-073-17/+19
| | | | llvm-svn: 183463
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-4/+4
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju2013-06-0419-154/+157
| | | | llvm-svn: 183243
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-034-0/+37
| | | | llvm-svn: 183094
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-032-0/+8
| | | | | | using two instructions (sethi and store). llvm-svn: 183090
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-021-22/+177
| | | | llvm-svn: 183088
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-021-1/+1
| | | | llvm-svn: 183083
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju2013-06-011-0/+6
| | | | | | as non-leaf functions. llvm-svn: 183079
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-014-30/+79
| | | | llvm-svn: 183067
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-2/+2
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-4/+6
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
* SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. ↵NAKAMURA Takumi2013-05-291-1/+1
| | | | | | [-Wunused-function] llvm-svn: 182850
* [Sparc] Add support for leaf functions in sparc backend. Venkatraman Govindaraju2013-05-296-28/+123
| | | | llvm-svn: 182822
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-253-28/+28
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Also expand 64-bit bitcasts.Jakob Stoklund Olesen2013-05-201-0/+2
| | | | llvm-svn: 182229
* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-201-2/+9
| | | | llvm-svn: 182228
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-201-0/+2
| | | | llvm-svn: 182227
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-192-4/+2
| | | | | | | | The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-191-0/+5
| | | | llvm-svn: 182224
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-191-0/+10
| | | | llvm-svn: 182222
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-192-27/+31
| | | | | | | Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
* [Sparc] Rearrange integer registers' allocation order so that register ↵Venkatraman Govindaraju2013-05-192-10/+23
| | | | | | | | allocator will use I and G registers before using L and O registers. Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode. llvm-svn: 182219
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-191-1/+1
| | | | llvm-svn: 182216
* [Sparc] Implements hasReservedCallFrame and hasFP.Venkatraman Govindaraju2013-05-172-1/+17
| | | | | | | This is to generate correct framesetup code when the function has variable sized allocas. llvm-svn: 182108
* [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay ↵Venkatraman Govindaraju2013-05-161-5/+9
| | | | | | slot. llvm-svn: 182063
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+1
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Remove unused argument.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181618
* Passing arguments to varags functions under the SPARC v9 ABI.Jakob Stoklund Olesen2013-04-211-0/+47
| | | | | | | Arguments after the fixed arguments never use the floating point registers. llvm-svn: 179987
* Fix the SETHIimm pattern for 64-bit code.Jakob Stoklund Olesen2013-04-211-2/+1
| | | | | | Don't ignore the high 32 bits of the immediate. llvm-svn: 179985
* Compile varargs functions for SPARCv9.Jakob Stoklund Olesen2013-04-201-31/+57
| | | | | | | | | | | | With a little help from the frontend, it looks like the standard va_* intrinsics can do the job. Also clean up an old bitcast hack in LowerVAARG that dealt with unaligned double loads. Load SDNodes can specify an alignment now. Still missing: Calling varargs functions with float arguments. llvm-svn: 179961
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-1/+0
| | | | llvm-svn: 179939
* Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen2013-04-162-0/+42
| | | | llvm-svn: 179582
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-144-7/+8
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen2013-04-141-0/+9
| | | | | | For when 16 TB just isn't enough. llvm-svn: 179474
* Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen2013-04-141-6/+16
| | | | | | | This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. llvm-svn: 179473
* Use target flags for printing SPARC asm operands.Jakob Stoklund Olesen2013-04-141-16/+34
| | | | | | | 64-bit code models need multiple relocations that can't be inferred from the opcode like they can in 32-bit code. llvm-svn: 179472
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-142-26/+36
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* Fix patterns for 64-bit pointers.Jakob Stoklund Olesen2013-04-141-4/+2
| | | | | | This fixes the pic32 code model for SPARC v9. llvm-svn: 179469
* Add target flags to SPARC address operands.Jakob Stoklund Olesen2013-04-143-14/+95
| | | | | | | | | SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. llvm-svn: 179468
* Define SPARC code models.Jakob Stoklund Olesen2013-04-132-4/+32
| | | | | | | Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. llvm-svn: 179463
* Use the correct types when matching ADDRri patterns from frame indexes.Jakob Stoklund Olesen2013-04-131-3/+4
| | | | | | | It doesn't seem like anybody is checking types this late in isel, so no test case. llvm-svn: 179462
* Extract a function.Jakob Stoklund Olesen2013-04-091-31/+17
| | | | llvm-svn: 179086
* Compute correct frame sizes for SPARC v9 64-bit frames.Jakob Stoklund Olesen2013-04-093-25/+40
| | | | | | | | | | The save area is twice as big and there is no struct return slot. The stack pointer is always 16-byte aligned (after adding the bias). Also eliminate the stack adjustment instructions around calls when the function has a reserved stack frame. llvm-svn: 179083
* Implement LowerCall_64 for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-072-0/+228
| | | | | | | There is still no support for byval arguments (which I don't think are needed) and varargs. llvm-svn: 178993
* Implement LowerReturn_64 for SPARC v9.Jakob Stoklund Olesen2013-04-063-9/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer return values are sign or zero extended by the callee, and structs up to 32 bytes in size can be returned in registers. The CC_Sparc64 CallingConv definition is shared between LowerFormalArguments_64 and LowerReturn_64. Function arguments and return values are passed in the same registers. The inreg flag is also used for return values. This is required to handle C functions returning structs containing floats and ints: struct ifp { int i; float f; }; struct ifp f(void); LLVM IR: define inreg { i32, float } @f() { ... ret { i32, float } %retval } The ABI requires that %retval.i is returned in the high bits of %i0 while %retval.f goes in %f1. Without the inreg return value attribute, %retval.i would go in %i0 and %retval.f would go in %f3 which is a more efficient way of returning %multiple values, but it is not ABI compliant for returning C structs. llvm-svn: 178966
* SPARC v9 stack pointer bias.Jakob Stoklund Olesen2013-04-062-2/+9
| | | | | | | | | | | 64-bit SPARC v9 processes use biased stack and frame pointers, so the current function's stack frame is located at %sp+BIAS .. %fp+BIAS where BIAS = 2047. This makes more local variables directly accessible via [%fp+simm13] addressing. llvm-svn: 178965
* Complete formal arguments for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-062-25/+178
| | | | | | | | | | | | | | | | | | | | | | | | All arguments are formally assigned to stack positions and then promoted to floating point and integer registers. Since there are more floating point registers than integer registers, this can cause situations where floating point arguments are assigned to registers after integer arguments that where assigned to the stack. Use the inreg flag to indicate 32-bit fragments of structs containing both float and int members. The three-way shadowing between stack, integer, and floating point registers requires custom argument lowering. The good news is that return values are passed in the exact same way, and we can share the code. Still missing: - Update LowerReturn to handle structs returned in registers. - LowerCall. - Variadic functions. llvm-svn: 178958
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-044-5/+35
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-035-5/+34
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-021-0/+68
| | | | | | There is only a few new instructions, the rest is handled with patterns. llvm-svn: 178528
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