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* Merged in autoconf branch. This provides configuration via the autoconfJohn Criswell2003-06-303-9/+18
| | | | | | system. llvm-svn: 7014
* Add the padding needed for variable-size alloca's, which should work now.Vikram S. Adve2003-06-231-6/+14
| | | | llvm-svn: 6859
* Some preprocessors doen't support // comments and get confusedChris Lattner2003-06-201-1/+1
| | | | llvm-svn: 6821
* RDCCR defines arg. #1, not arg. #2.Vikram S. Adve2003-06-201-1/+1
| | | | llvm-svn: 6796
* lib/Target/Sparc/Sparc.cpp:Brian Gaeke2003-06-181-1/+22
| | | | | | | | | | | | | | | | | | | | | Move LowerAllocations, PrintFunction, and SymbolStripping passes, and the corresponding -disable-strip and -d options, over here to the SPARC target-specific bits of llc. Rename -d to -dump-asm. tools/llc/Makefile: Reindent. Add x86 library so that llc compiles again. tools/llc/llc.cpp: Remove support for running arbitrary optimization passes. Use opt instead. Remove LowerAllocations, PrintFunction, and SymbolStripping passes, as noted above. Allow user to select a backend (x86 or SPARC); default to guessing from the endianness/pointer size of the input bytecode file. Fix typos. Delete empty .s file and exit with error status if target does not support static compilation. llvm-svn: 6776
* These instructions really take three operands. This fixes some assertionsChris Lattner2003-06-181-2/+2
| | | | llvm-svn: 6765
* Rename FInfo.cpp to FunctionInfo.cpp, eliminate FInfo.hChris Lattner2003-06-161-2/+0
| | | | llvm-svn: 6712
* move contents of include/llvm/Reoptimizer/Mapping/FInfo.h into here, it is ↵Chris Lattner2003-06-161-0/+2
| | | | | | sparc internal llvm-svn: 6711
* Fix invalid number of arguments problemChris Lattner2003-06-161-2/+2
| | | | llvm-svn: 6692
* Updated for the new projects Makefile.John Criswell2003-06-111-4/+4
| | | | llvm-svn: 6678
* Print address out as hex.Misha Brukman2003-06-061-1/+1
| | | | llvm-svn: 6657
* Added 'r' and 'i' versions to WRCCR.Misha Brukman2003-06-061-1/+2
| | | | llvm-svn: 6656
* * Changed Bcc instructions to behave like BPcc instructionsMisha Brukman2003-06-067-38/+64
| | | | | | | | | * BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes llvm-svn: 6655
* * Removed PreSelection pass because that is now done in the JITMisha Brukman2003-06-061-22/+10
| | | | | | | * Removed instruction scheduling as it is too slow to run in a JIT environment * Removed other passes because they aren't necessary and can slow JIT down llvm-svn: 6652
* Fixed a bunch of test cases in test/Regression/Jello which could not get theMisha Brukman2003-06-061-2/+13
| | | | | | address of a floating-point (allocated via ConstantPool) correctly. llvm-svn: 6647
* * If a global is not a function, just ask the MachineCodeEmitter for the addrMisha Brukman2003-06-061-3/+3
| | | | | | * Do not block a print statement with a DEBUG() guard if we're going to abort() llvm-svn: 6645
* The SUB*i instructions belong to a different class than their SUB*r brethren.Misha Brukman2003-06-061-4/+4
| | | | llvm-svn: 6644
* Put all debug print statements under the DEBUG() guard to make output clean soMisha Brukman2003-06-061-35/+36
| | | | | | that tests can automatically diff the output. llvm-svn: 6642
* Fixed confusion between register classes and register types.Misha Brukman2003-06-051-2/+4
| | | | | | Now %fcc registers are recognized correctly. llvm-svn: 6640
* Added missing directive to store the instruction name.Misha Brukman2003-06-051-0/+1
| | | | llvm-svn: 6639
* Moved predict and annul fields to the end of each individual instructionMisha Brukman2003-06-051-12/+15
| | | | | | class, because they are currently unused. llvm-svn: 6638
* Do not preset the cc register, the instructions actually use it.Misha Brukman2003-06-051-20/+17
| | | | llvm-svn: 6637
* Minor tuning -- avoid a non-inlinable function call on every operand.Vikram S. Adve2003-06-051-70/+72
| | | | | | Also, reorder a couple of functions for inlining. llvm-svn: 6635
* Added lazy function resolution to the JIT.Misha Brukman2003-06-052-31/+223
| | | | llvm-svn: 6633
* * The textual output of (non-)predicted FP branches is the same.Misha Brukman2003-06-051-24/+50
| | | | | | | * Stop mapping FBcc instructions to deprecated opcodes, map to FBPcc instead. * Fixed opf in FCMPxy instructions. llvm-svn: 6632
* All store instructions really want 'rd' in the first field.Misha Brukman2003-06-051-13/+20
| | | | | | | | Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and expect %fsr as the parameter in assembly. They are disabled (since not used) until an encoding, both for code generation and output, is chosen. llvm-svn: 6619
* Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2.Misha Brukman2003-06-051-3/+2
| | | | llvm-svn: 6618
* lib/CodeGen/Mapping/MappingInfo.cpp:Brian Gaeke2003-06-042-109/+117
| | | | | | | | | | | | | | | | | | | | Update file comment to contain a bunch of the overview mapping-info documentation previously buried within the file. Remove some unnecessary include/using stmts. Rename pass to MappingInfoCollector. Rewrite a lot of it so it doesn't use global instance variables and so it outputs into MappingInfo objects and then dumps those out, instead of going straight to an assembly file. Change name of factory to getMappingInfoCollector. Fold prologue & epilogue writers into MappingInfo methods. lib/Target/Sparc/FInfo.cpp: Correct file comment to reflect above change lib/Target/Sparc/Sparc.cpp: Change name of factory to getMappingInfoCollector. llvm-svn: 6617
* Add file comment. Include <vector> and <string>. Update include guardsBrian Gaeke2003-06-041-5/+32
| | | | | | | to reflect file's current location. Add definition of class MappingInfo. llvm-svn: 6616
* Revert brians patch to get mapping info working againChris Lattner2003-06-041-9/+4
| | | | | | sorry dude llvm-svn: 6615
* Had to comment out a line in outByte() to get it to compile because Out and ↵Tanya Lattner2003-06-041-1/+1
| | | | | | | | tmp were undeclared. I was not sure what Brian wanted, so I will let him fix this. But now it compiles. llvm-svn: 6614
* * Instead of re-inventing the MachineConstantPool emitter that's already givenMisha Brukman2003-06-042-111/+146
| | | | | | | | | | | | | | | | | | | | in Emitter.cpp, just convert the Sparc version of the constant pool into what's already supported and inter-operate. * Implemented a first pass at lazy function resolution in the JITResolver. That required adding a SparcV9CodeEmitter pointer to simplify generating bit-patterns of the instructions. * SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and lives for the entire duration of the JIT (via PassManager which lives in VM). * Changed all return values in the JITResolver to uint64_t because of the 64-bit Sparc architecture. * Added a new version of getting the value of a GlobalValue in the SparcV9CodeEmitter, which now works for already-generated functions (JITted or library functions). * Removed little-used and unused functions, cleaning up the internal view of the SparcV9CodeEmitter. llvm-svn: 6612
* Make writeNumber() void. Get ready to decouple it from .byte directive output.Brian Gaeke2003-06-041-4/+9
| | | | llvm-svn: 6609
* Added the 4.7 instruction class and all the FMOVcc instructions in them.Misha Brukman2003-06-042-37/+130
| | | | llvm-svn: 6601
* Comment out opcodes currently unused in the Sparc backend.Misha Brukman2003-06-041-0/+3
| | | | llvm-svn: 6597
* Added instruction format class 3.15 and floating-point compare instructions.Misha Brukman2003-06-042-11/+22
| | | | llvm-svn: 6594
* Avoid generating a getelementptr instruction of a functionChris Lattner2003-06-041-1/+1
| | | | llvm-svn: 6591
* Make the write*map methods more self-contained. Document some more.Brian Gaeke2003-06-031-42/+57
| | | | llvm-svn: 6589
* I documented this file, in an attempt to understand it, with a view towardBrian Gaeke2003-06-031-56/+73
| | | | | | | | | | | rewriting it. I also vacuumed out all the commented-out code and inaccurate comments, etc. (We need to put the mapping information in a data structure so that we can pass it out to the JIT, instead of automagically converting it to .byte directives.) llvm-svn: 6574
* Use the new -o tablegen optionChris Lattner2003-06-031-4/+1
| | | | llvm-svn: 6572
* Constants are laid out in memory in PC-relative form.Misha Brukman2003-06-031-1/+1
| | | | llvm-svn: 6568
* Added opcode conversion for conditional move of integers.Misha Brukman2003-06-031-0/+50
| | | | llvm-svn: 6567
* * Convert load/store opcodes from register to immediate forms.Misha Brukman2003-06-031-9/+11
| | | | | | * Stop code from wrapping to the next line. llvm-svn: 6566
* Convert load/store opcodes from register to immediate forms, if necessary.Misha Brukman2003-06-031-4/+13
| | | | llvm-svn: 6565
* Store instructions are different from other Format 3.1/3.2 instructions in thatMisha Brukman2003-06-032-7/+43
| | | | | | | they prefer the destination register to be last. Thus, two new classes were made for them that accomodate for having this layout of operands (F3_1rd, F3_2rd). llvm-svn: 6564
* * Added section A.34: Move FP register on int reg condition (FMOVr)Misha Brukman2003-06-031-13/+42
| | | | | | | * Labeled sections that are not currently used in the Sparc backend as not requiring completion at this time. llvm-svn: 6562
* * Removed unused classes (rd field is always mentioned last); fixed comments.Misha Brukman2003-06-031-38/+34
| | | | | | | * Added instruction classes which start building from rs1, then rs2, and rd. * Fixed order of operands in classes 4.1 and 4.2; added 4.6 . llvm-svn: 6561
* * Removed unused classes: the rd field is always mentioned as the last reg.Misha Brukman2003-06-031-57/+19
| | | | | | | | | * Added new classes which start building from rs1, adding rs2, and then rd. * Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 . * Fixed comments to reflect Real Life (tm). * Removed "don't care" commented out assignments and dead classes (#if 0). llvm-svn: 6560
* The rd field goes after the immediate field in format 2.1 instructions.Misha Brukman2003-06-031-2/+1
| | | | llvm-svn: 6559
* Added MOVR (move int reg on register condition), aka comparison with zero.Misha Brukman2003-06-023-8/+48
| | | | | | | None of these instructions are actually used in the Sparc backend, so no changes were required in the instruction selector. llvm-svn: 6549
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