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path: root/llvm/lib/Target/Sparc/SparcInstrInfo.td
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* [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MULHU/MUL.James Y Knight2016-10-051-2/+2
* [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> froundMichael Kuperstein2016-08-181-10/+10
* [SPARC] Fixes for hardware errata on LEON processor.Chris Dewhurst2016-06-191-0/+13
* [SPARC] Fix 8 and 16-bit atomic load and store.James Y Knight2016-05-231-9/+17
* [Sparc][LEON] Add LEON-specific CASA instruction.Chris Dewhurst2016-05-161-6/+27
* [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargetsChris Dewhurst2016-05-091-0/+28
* [Sparc] Implement __builtin_setjmp, __builtin_longjmp back-end.Chris Dewhurst2016-05-041-0/+31
* [Sparc] This provides support for itineraries on Sparc.Chris Dewhurst2016-04-221-112/+178
* This change adds co-processor condition branching and conditional traps to th...Chris Dewhurst2016-03-091-1/+13
* The patch adds missing registers and instructions to complete all the registe...Chris Dewhurst2016-02-271-14/+90
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-261-83/+6
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-261-6/+83
* Start replacing vector_extract/vector_insert with extractelt/inserteltMatt Arsenault2015-12-111-2/+2
* [SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger2015-10-041-0/+19
* [SPARC] Add mulscc.Joerg Sonnenberger2015-09-171-0/+4
* [SPARC] Recognize st/stx operations with %fsr argument too.Joerg Sonnenberger2015-09-161-0/+16
* [Sparc]: asm-only support for the ldstub instruction.Douglas Katzman2015-08-191-0/+11
* [SPARC] Enable writing to floating-point-state register.Douglas Katzman2015-08-191-0/+16
* [Sparc] Rename LoadASR and StoreASR from r245360 to *ASI, as was intended.James Y Knight2015-08-191-10/+10
* Load/store instructions for floating points with address space require SparcV9.Joerg Sonnenberger2015-08-181-19/+39
* Load/store for float registers from/to alternate space.Joerg Sonnenberger2015-08-101-6/+6
* [Sparc] Implement i64 load/store support for 32-bit sparc.James Y Knight2015-08-101-0/+18
* [Sparc] Fix disassembly of popc instruction.James Y Knight2015-08-051-2/+2
* [SPARC] Cleanup handling of the Y/ASR registers.James Y Knight2015-07-081-2/+2
* [Sparc] Add more instruction aliases.James Y Knight2015-07-061-0/+1
* [Sparc] Add support for flush instruction.James Y Knight2015-07-061-0/+14
* [Sparc] Rearrange SparcInstrInfo, no change.James Y Knight2015-07-011-68/+80
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-181-0/+48
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-181-10/+41
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-181-12/+11
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-2/+3
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-3/+2
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-2/+3
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-9/+9
* Fix a whole bunch of binary literals which were the wrong size. All were bei...Pete Cooper2014-08-071-1/+1
* [Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju2014-03-091-1/+1
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc back...Venkatraman Govindaraju2014-03-021-0/+12
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-021-0/+8
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-021-1/+2
* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-021-0/+13
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-021-1/+7
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ...Venkatraman Govindaraju2014-03-021-0/+4
* [Sparc] Add support for parsing branches and conditional move instructions wi...Venkatraman Govindaraju2014-03-021-1/+29
* [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 ...Venkatraman Govindaraju2014-03-021-16/+20
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-021-1/+14
* [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).Venkatraman Govindaraju2014-03-021-5/+5
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-011-18/+49
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-011-6/+27
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-011-1/+2
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+35
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