| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Change latencies for Load, Store and Branch instructions. | Vikram S. Adve | 2002-03-24 | 1 | -40/+42 |
| * | Change latency of SETX to improve schedule -- just a hack. | Vikram S. Adve | 2001-11-14 | 1 | -1/+1 |
| * | Added M_PSEUDO_FLAG for SETX .. instr | Ruchira Sasanka | 2001-11-14 | 1 | -3/+3 |
| * | Fixed instruction information for RDCCR and WRCCR. | Vikram S. Adve | 2001-11-04 | 1 | -4/+3 |
| * | Added code to support correct saving of %ccr across calls | Ruchira Sasanka | 2001-11-03 | 1 | -0/+6 |
| * | Add SETX instruction for 64-bit constants. | Vikram S. Adve | 2001-10-28 | 1 | -8/+9 |
| * | Added SAVE and RESTORE. Duplicated JMPL into JMPLCALL and JMPLRET, | Vikram S. Adve | 2001-10-22 | 1 | -1/+6 |
| * | Change latency of setuw and setsw to 2 cycles. | Vikram S. Adve | 2001-09-30 | 1 | -4/+5 |
| * | Seperate instruction definitions into new SparcInstr.def file | Chris Lattner | 2001-09-19 | 1 | -0/+440 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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