summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Sparc/SparcISelLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [Sparc] Add support for 13-bit PICDaniel Cederman2018-06-111-4/+15
| | | | | | | | | | | | | | | | | Summary: When compiling with -fpic, in contrast to -fPIC, use only the immediate field to index into the GOT. This saves space if the GOT is known to be small. The linker will warn if the GOT is too large for this method. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: brad, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47136 llvm-svn: 334383
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-0/+5
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [Sparc] Treat %fxx registers with value type Other as single precisionDaniel Cederman2018-05-301-1/+1
| | | | | | | They get type Other when used in the clobber list in inline assembly. This fixes tests fp128.ll and float.ll that failed after r333512. llvm-svn: 333523
* [Sparc] Select correct register class for FP register constraintsDaniel Cederman2018-05-301-0/+16
| | | | | | | | | | | | | | | | | Summary: The fX version of floating-point registers only supports single precision. We need to map the name to dX for doubles and qX for long doubles if we want getRegForInlineAsmConstraint() to be able to pick the correct register class. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47258 llvm-svn: 333512
* TargetMachine: Add address space to getPointerSizeMatt Arsenault2018-03-141-1/+1
| | | | llvm-svn: 327467
* [TLS] use emulated TLS if the target supports only this modeChih-Hung Hsieh2018-02-281-1/+1
| | | | | | | | | | | | | | | Emulated TLS is enabled by llc flag -emulated-tls, which is passed by clang driver. When llc is called explicitly or from other drivers like LTO, missing -emulated-tls flag would generate wrong TLS code for targets that supports only this mode. Now use useEmulatedTLS() instead of Options.EmulatedTLS to decide whether emulated TLS code should be generated. Unit tests are modified to run with and without the -emulated-tls flag. Differential Revision: https://reviews.llvm.org/D42999 llvm-svn: 326341
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-6/+6
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversionRichard Trieu2017-12-111-73/+19
| | | | | | | | See bug https://bugs.llvm.org/show_bug.cgi?id=35631 r318704 is giving a fatal error on some code with unsigned to floating point conversions. llvm-svn: 320429
* [Sparc] efficient pattern for UINT_TO_FP conversionFedor Sergeev2017-11-201-19/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: while investigating performance degradation of imagick benchmark there were found inefficient pattern for UINT_TO_FP conversion. That pattern causes RAW hazard in assembly code. Specifically, uitofp IR operator results in poor assembler : st %i0, [%fp - 952] ldd [%fp - 952], %f0 it stores 32-bit integer register into memory location and then loads 64-bit floating point data from that location. That is exactly RAW hazard case. To optimize that case it is possible to use SPISD::ITOF and SPISD::XTOF for conversion from integer to floating point data type and to use ISD::BITCAST to copy from integer register into floating point register. The fix is to write custom UINT_TO_FP pattern using SPISD::ITOF, SPISD::XTOF, ISD::BITCAST. Patch by Alexey Lapshin Reviewers: fedor.sergeev, jyknight, dcederman, lero_chris Reviewed By: jyknight Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36875 llvm-svn: 318704
* [Sparc][NFC] Clean up SelectCC loweringAlex Bradbury2017-09-071-44/+40
| | | | | | | | | | | | | | The ARM, BPF, MSP430, Sparc and Mips backends all use a similar code sequence for lowering SelectCC. As pointed out by @reames in D29937, this code isn't particularly clear and in most of these backends doesn't actually match the comments. This patch makes the code sequence clearer for the Sparc backend through better variable naming and more accurate comments (e.g. we are inserting triangle control flow, _not_ diamond). There is no functional change. Differential Revision: https://reviews.llvm.org/D37194 llvm-svn: 312713
* Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. ↵Peter Collingbourne2017-07-261-3/+3
| | | | | | | | NFCI. This was a use-after-free waiting to happen. llvm-svn: 309159
* [SPARC] Clean up the support for disabling fsmuld and fmuls instructions.James Y Knight2017-07-201-3/+1
| | | | | | | | | | | | | | | | | Summary: Also enable no-fsmuld for sparcv7 (which doesn't have the instruction). The previous code which used a post-processing pass to do this was unnecessary; disabling the instruction is entirely sufficient. Reviewers: jacob_hansen, ekedaigle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35576 llvm-svn: 308661
* [Sparc] Added software multiplication/division featureJames Y Knight2017-07-181-0/+13
| | | | | | | | | | | Added a feature to the Sparc back-end that replaces the integer multiply and divide instructions with calls to .mul/.sdiv/.udiv. This is a step towards having full v7 support. Patch by: Eric Kedaigle Differential Revision: https://reviews.llvm.org/D35500 llvm-svn: 308343
* [SPARC] Support 'f' and 'e' inline asm constraints.James Y Knight2017-05-121-1/+22
| | | | | | | | Based on patch by Patrick Boettcher and Chris Dewhurst. Differential Revision: https://reviews.llvm.org/D29116 llvm-svn: 302911
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* [KnownBits] Add wrapper methods for setting and clear all bits in the ↵Craig Topper2017-05-051-1/+1
| | | | | | | | | | underlying APInts in KnownBits. This adds routines for reseting KnownBits to unknown, making the value all zeros or all ones. It also adds methods for querying if the value is zero, all ones or unknown. Differential Revision: https://reviews.llvm.org/D32637 llvm-svn: 302262
* [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and ↵Craig Topper2017-04-281-8/+8
| | | | | | | | | | | | simplifyDemandedBits This patch replaces the separate APInts for KnownZero/KnownOne with a single KnownBits struct. This is similar to what was done to ValueTracking's version recently. This is largely a mechanical transformation from KnownZero to Known.Zero. Differential Revision: https://reviews.llvm.org/D32569 llvm-svn: 301620
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301234
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-241-3/+1
| | | | | | I forgot to commit local changes before commit. llvm-svn: 301232
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301231
* [DAGCombiner] Add vector demanded elements support to ↵Simon Pilgrim2017-03-311-0/+1
| | | | | | | | | | computeKnownBitsForTargetNode Follow up to D25691, this sets up the plumbing necessary to support vector demanded elements support in known bits calculations in target nodes. Differential Revision: https://reviews.llvm.org/D31249 llvm-svn: 299201
* Capitalize ArgListEntry fields. NFC.Nirav Dave2017-03-181-2/+2
| | | | llvm-svn: 298178
* Fix typo in comment. NFC.Simon Pilgrim2016-11-181-1/+1
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287331
* [Sparc] Don't overlap variable-sized allocas with other stack variables.James Y Knight2016-10-251-3/+43
| | | | | | | | | | | | | | | | | | | | On SparcV8, it was previously the case that a variable-sized alloca might overlap by 4-bytes the last fixed stack variable, effectively because 92 (the number of bytes reserved for the register spill area) != 96 (the offset added to SP for where to start a DYNAMIC_STACKALLOC). It's not as simple as changing 96 to 92, because variables that should be 8-byte aligned would then be misaligned. For now, simply increase the allocation size by 8 bytes for each dynamic allocation -- wastes space, but at least doesn't overlap. As the large comment says, doing this more efficiently will require larger changes in llvm. Also adds some test cases showing that we continue to not support dynamic stack allocation and over-alignment in the same function. llvm-svn: 285131
* [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MULHU/MUL.James Y Knight2016-10-051-3/+4
| | | | | | | This is what the instruction-set actually provides, and the default expansions of the others into the lohi opcodes are good. llvm-svn: 283381
* [Sparc][Leon] Corrected supported atomics size for processors supporting ↵Chris Dewhurst2016-09-061-1/+1
| | | | | | | | Leon CASA instruction back to 32 bits. This was erroneously checked-in for 64 bits while trying to find if there was a way to get 64 bit atomicity in Leon processors. There is not and this change should not have been checked-in. There is no unit test for this as the existing unit tests test for behaviour to 32 bits, which was the original intention of the code. llvm-svn: 280710
* [Sparc] Mark i128 shift libcalls unavailable in 32-bit mode.James Y Knight2016-09-021-0/+7
| | | | | | | | | | | Recently, llvm wants to emit calls to these functions, while it didn't seem to be an issue before. Not sure why. Nor do I know why only these three are important to disable, out of all of the i128 libcalls. Nevertheless, many other targets have this snippet of code, so, just copying it to sparc as well, to unbreak things. llvm-svn: 280537
* [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> froundMichael Kuperstein2016-08-181-1/+1
| | | | | | | | | | The names of the tablegen defs now match the names of the ISD nodes. This makes the world a slightly saner place, as previously "fround" matched ISD::FP_ROUND and not ISD::FROUND. Differential Revision: https://reviews.llvm.org/D23597 llvm-svn: 279129
* Revert "[Sparc] Leon errata fix passes."James Y Knight2016-08-121-10/+9
| | | | | | | | | | | ...and the two followup commits: Revert "[Sparc][Leon] Missed resetting option flags from check-in 278489." Revert "[Sparc][Leon] Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor." This reverts commit r274856, r278489, and r278492. llvm-svn: 278511
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-33/+33
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [Sparc]: Fix bug in LowerSTORE due to r275592Douglas Katzman2016-07-211-1/+1
| | | | llvm-svn: 276362
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-151-115/+66
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [Sparc] Leon errata fix passes.Chris Dewhurst2016-07-081-9/+10
| | | | | | | | | | | | Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-021-7/+6
| | | | | | | | where possible. No functionality change intended. llvm-svn: 274431
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-301-27/+25
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* [Sparc] Atomics pass changes to make work with SparcV8 back-ends.Chris Dewhurst2016-06-271-4/+2
| | | | | | This change reverts a "false" test that was placed to avoid regressions while the atomics pass was completed for the Sparc back-ends. llvm-svn: 273949
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-271-2/+2
| | | | llvm-svn: 273907
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-271-4/+2
| | | | llvm-svn: 273903
* [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCalleeKrzysztof Parzyszek2016-06-221-2/+2
| | | | | | | | | | | The setCallee function will set the number of fixed arguments based on the size of the argument list. The FixedArgs parameter was often explicitly set to 0, leading to a lack of consistent value for non- vararg functions. Differential Revision: http://reviews.llvm.org/D20376 llvm-svn: 273403
* [SPARC] Fixes for hardware errata on LEON processor.Chris Dewhurst2016-06-191-0/+13
| | | | | | | | | | Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
* Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass.James Y Knight2016-06-171-0/+2
| | | | | | | | | | | | | | | | | Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-44/+30
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [Sparc] Allow passing of empty structs.Chris Dewhurst2016-06-011-11/+21
| | | | | | | | Passing an empty struct as a function call argument is now supported. unit tests for various scenarios added. llvm-svn: 271374
* Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer2016-05-271-1/+2
| | | | | | | Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982
* [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.Chris Dewhurst2016-05-231-2/+2
| | | | | | | | | | Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 llvm-svn: 270417
* SparcISelLowering.cpp: Add missing StringSwitch.hNAKAMURA Takumi2016-05-201-0/+1
| | | | llvm-svn: 270200
* [Sparc] Implement getRegisterByName.Chris Dewhurst2016-05-201-0/+21
| | | | | | Allows Sparc registers to be specifically referred to in inline assembly. llvm-svn: 270198
* [Sparc] Add Soft Float supportChris Dewhurst2016-05-181-5/+11
| | | | | | | | | | This change adds support for software floating point operations for Sparc targets. This is the first in a set of patches to enable software floating point on Sparc. The next patch will enable the option to be used with Clang. Differential Revision: http://reviews.llvm.org/D19265 llvm-svn: 269892
* [Sparc][LEON] Add LEON-specific CASA instruction.Chris Dewhurst2016-05-161-6/+7
| | | | | | Differental Revision: http://reviews.llvm.org/D20098 llvm-svn: 269644
* [Sparc] Implement __builtin_setjmp, __builtin_longjmp back-end.Chris Dewhurst2016-05-041-21/+249
| | | | | | | | | | | | | | This code implements builtin_setjmp and builtin_longjmp exception handling intrinsics for 32-bit Sparc back-ends. The code started as a mash-up of the PowerPC and X86 versions, although there are sufficient differences to both that had to be made for Sparc handling. Note: I have manual tests running. I'll work on a unit test and add that to the rest of this diff in the next day. Also, this implementation is only for 32-bit Sparc. I haven't focussed on a 64-bit version, although I have left the code in a prepared state for implementing this, including detecting pointer size and comments indicating where I suspect there may be differences. Differential Revision: http://reviews.llvm.org/D19798 llvm-svn: 268483
OpenPOWER on IntegriCloud