CodeGen: Use MachineInstr& in TargetLowering, NFC

This is a mechanical change to make TargetLowering API take MachineInstr&
(instead of MachineInstr*), since the argument is expected to be a valid
MachineInstr.  In one case, changed a parameter from MachineInstr* to
MachineBasicBlock::iterator, since it was used as an insertion point.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

llvm-svn: 274287

1 files changed, 25 insertions, 27 deletions

diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 362305390c9..1a5857098f6 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3092,9 +3092,9 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 }
 
 MachineBasicBlock *
-SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
+SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                  MachineBasicBlock *BB) const {
-  switch (MI->getOpcode()) {
+  switch (MI.getOpcode()) {
   default: llvm_unreachable("Unknown SELECT_CC!");
   case SP::SELECT_CC_Int_ICC:
   case SP::SELECT_CC_FP_ICC:
@@ -3116,13 +3116,12 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   }
 }
 
-MachineBasicBlock*
-SparcTargetLowering::expandSelectCC(MachineInstr *MI,
-                                    MachineBasicBlock *BB,
+MachineBasicBlock *
+SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
                                     unsigned BROpcode) const {
   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
-  DebugLoc dl = MI->getDebugLoc();
-  unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
+  DebugLoc dl = MI.getDebugLoc();
+  unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
 
   // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
   // control-flow pattern.  The incoming instruction knows the destination vreg
@@ -3167,20 +3166,20 @@ SparcTargetLowering::expandSelectCC(MachineInstr *MI,
   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
   //  ...
   BB = sinkMBB;
-  BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
-    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
-    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
+  BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI.getOperand(0).getReg())
+      .addReg(MI.getOperand(2).getReg())
+      .addMBB(copy0MBB)
+      .addReg(MI.getOperand(1).getReg())
+      .addMBB(thisMBB);
 
-  MI->eraseFromParent();   // The pseudo instruction is gone now.
+  MI.eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }
 
-
-MachineBasicBlock* SparcTargetLowering::
-emitEHSjLjLongJmp(MachineInstr *MI,
-                  MachineBasicBlock *MBB) const
-{
-  DebugLoc DL = MI->getDebugLoc();
+MachineBasicBlock *
+SparcTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
+                                       MachineBasicBlock *MBB) const {
+  DebugLoc DL = MI.getDebugLoc();
   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
 
   MachineFunction *MF = MBB->getParent();
@@ -3191,7 +3190,7 @@ emitEHSjLjLongJmp(MachineInstr *MI,
   unsigned RegSize = PVT.getStoreSize();
   assert(PVT == MVT::i32 && "Invalid Pointer Size!");
 
-  unsigned Buf = MI->getOperand(0).getReg();
+  unsigned Buf = MI.getOperand(0).getReg();
   unsigned JmpLoc = MRI.createVirtualRegister(&SP::IntRegsRegClass);
 
   // TO DO: If we do 64-bit handling, this perhaps should be FLUSHW, not TA 3
@@ -3226,15 +3225,14 @@ emitEHSjLjLongJmp(MachineInstr *MI,
   // Jump to JmpLoc
   BuildMI(*MBB, MI, DL, TII->get(SP::JMPLrr)).addReg(SP::G0).addReg(JmpLoc, RegState::Kill).addReg(SP::G0);
 
-  MI->eraseFromParent();
+  MI.eraseFromParent();
   return MBB;
 }
 
-MachineBasicBlock* SparcTargetLowering::
-emitEHSjLjSetJmp(MachineInstr *MI,
-                 MachineBasicBlock *MBB) const
-{
-  DebugLoc DL = MI->getDebugLoc();
+MachineBasicBlock *
+SparcTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
+                                      MachineBasicBlock *MBB) const {
+  DebugLoc DL = MI.getDebugLoc();
   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
 
   MachineFunction *MF = MBB->getParent();
@@ -3245,7 +3243,7 @@ emitEHSjLjSetJmp(MachineInstr *MI,
   unsigned RegSize = PVT.getStoreSize();
   assert(PVT == MVT::i32 && "Invalid Pointer Size!");
 
-  unsigned DstReg = MI->getOperand(0).getReg();
+  unsigned DstReg = MI.getOperand(0).getReg();
   const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
   assert(RC->hasType(MVT::i32) && "Invalid destination!");
   unsigned mainDstReg = MRI.createVirtualRegister(RC);
@@ -3292,7 +3290,7 @@ emitEHSjLjSetJmp(MachineInstr *MI,
 
   unsigned LabelReg = MRI.createVirtualRegister(&SP::IntRegsRegClass);
   unsigned LabelReg2 = MRI.createVirtualRegister(&SP::IntRegsRegClass);
-  unsigned BufReg = MI->getOperand(1).getReg();
+  unsigned BufReg = MI.getOperand(1).getReg();
 
   // Instruction to store FP
   const unsigned FP  = SP::I6;
@@ -3371,7 +3369,7 @@ emitEHSjLjSetJmp(MachineInstr *MI,
              .addReg(mainDstReg).addMBB(mainMBB)
              .addReg(restoreDstReg).addMBB(restoreMBB);
 
-  MI->eraseFromParent();
+  MI.eraseFromParent();
   return sinkMBB;
 }