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* [Sparc] Implement i64 load/store support for 32-bit sparc.James Y Knight2015-08-101-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LDD/STD instructions can load/store a 64bit quantity from/to memory to/from a consecutive even/odd pair of (32-bit) registers. They are part of SparcV8, and also present in SparcV9. (Although deprecated there, as you can store 64bits in one register). As recommended on llvmdev in the thread "How to enable use of 64bit load/store for 32bit architecture" from Apr 2015, I've modeled the 64-bit load/store operations as working on a v2i32 type, rather than making i64 a legal type, but with few legal operations. The latter does not (currently) work, as there is much code in llvm which assumes that if i64 is legal, operations like "add" will actually work on it. The same assumption does not hold for v2i32 -- for vector types, it is workable to support only load/store, and expand everything else. This patch: - Adds a new register class, IntPair, for even/odd pairs of registers. - Modifies the list of reserved registers, the stack spilling code, and register copying code to support the IntPair register class. - Adds support in AsmParser. (note that in asm text, you write the name of the first register of the pair only. So the parser has to morph the single register into the equivalent paired register). - Adds the new instructions themselves (LDD/STD/LDDA/STDA). - Hooks up the instructions and registers as a vector type v2i32. Adds custom legalizer to transform i64 load/stores into v2i32 load/stores and bitcasts, so that the new instructions can actually be generated, and marks all operations other than load/store on v2i32 as needing to be expanded. - Copies the unfortunate SelectInlineAsm hack from ARMISelDAGToDAG. This hack undoes the transformation of i64 operands into two arbitrarily-allocated separate i32 registers in SelectionDAGBuilder. and instead passes them in a single IntPair. (Arbitrarily allocated registers are not useful, asm code expects to be receiving a pair, which can be passed to ldd/std.) Also adds a bunch of test cases covering all the bugs I've added along the way. Differential Revision: http://reviews.llvm.org/D8713 llvm-svn: 244484
* [SPARC] Don't compare arch name as a string, use the enum instead.Douglas Katzman2015-08-061-1/+1
| | | | | | Fixes PR22695 llvm-svn: 244221
* [llvm-mc] Pushing plumbing through for --fatal-warnings flag.Colin LeMahieu2015-07-271-1/+1
| | | | llvm-svn: 243334
* Reverting r241058 because it's causing buildbot failures.Ranjeet Singh2015-06-301-4/+1
| | | | llvm-svn: 241061
* There are a few places where subtarget features are stillRanjeet Singh2015-06-301-1/+4
| | | | | | | | | represented by uint64_t, this patch replaces these usages with the FeatureBitset (std::bitset) type. Differential Revision: http://reviews.llvm.org/D10542 llvm-svn: 241058
* [SPARC] Repair GOT references to internal symbols.James Y Knight2015-06-181-0/+9
| | | | | | | | | | They had been getting emitted as a section + offset reference, which is bogus since the value needs to be the offset within the GOT, not the actual address of the symbol's object. Differential Revision: http://reviews.llvm.org/D10441 llvm-svn: 240020
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-101-1/+3
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-6/+6
| | | | llvm-svn: 238634
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-1/+1
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* Sparc: support the "set" synthetic instruction.James Y Knight2015-05-181-2/+60
| | | | | | | | | This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 llvm-svn: 237585
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-181-8/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-181-0/+9
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-181-5/+19
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-7/+7
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [Sparc] Really add sparcel architecture support.Douglas Katzman2015-04-291-1/+1
| | | | | | | | Mostly copy-and-paste from Sparc v8 architecture. Differential Revision: http://reviews.llvm.org/D8741 llvm-svn: 236146
* Make Sparc assembler accept parenthesized constant expressions.Douglas Katzman2015-04-291-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D9087 llvm-svn: 236137
* Sparc: Prefer reg+reg address encoding when only one register used.James Y Knight2015-04-291-5/+5
| | | | | | | | | | | Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces. Futhermore, reg+imm is invalid for the (not yet supported) "alternate address space" instructions. Differential Revision: http://reviews.llvm.org/D8753 llvm-svn: 236107
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-4/+1
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-4/+4
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-181-1/+1
| | | | llvm-svn: 211141
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-82/+69
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-14/+14
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition llvm-svn: 207502
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207394
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-9/+9
| | | | llvm-svn: 207197
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-101-1/+1
| | | | llvm-svn: 205961
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-021-0/+6
| | | | llvm-svn: 202666
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-021-14/+3
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-021-7/+14
| | | | llvm-svn: 202610
* [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).Venkatraman Govindaraju2014-03-021-2/+2
| | | | llvm-svn: 202604
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-011-0/+31
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-011-6/+2
| | | | llvm-svn: 202598
* [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.Venkatraman Govindaraju2014-03-011-3/+51
| | | | llvm-svn: 202571
* [Sparc] Add support for parsing directives in SparcAsmParser.Venkatraman Govindaraju2014-03-011-2/+48
| | | | llvm-svn: 202564
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-071-1/+18
| | | | | | parsing CAS instructions to test the CAS encoding. llvm-svn: 200963
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-1/+1
| | | | llvm-svn: 200345
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-241-1/+1
| | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
* Fix out of bounds access to the double regs array. Given theEric Christopher2014-01-231-1/+1
| | | | | | | code this looks correct, but could use review. The previous was definitely not correct. llvm-svn: 199940
* [Sparc] Add support for parsing floating point instructions.Venkatraman Govindaraju2014-01-121-23/+97
| | | | llvm-svn: 199033
* [Sparc] Add support for parsing jmpl instruction and make indirect call and ↵Venkatraman Govindaraju2014-01-101-0/+1
| | | | | | jmp instructions as aliases to jmpl. llvm-svn: 198909
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-081-1/+21
| | | | llvm-svn: 198738
* [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc., Venkatraman Govindaraju2014-01-071-5/+35
| | | | | | Also, correct the offsets for FixupsKindInfo. llvm-svn: 198681
* [Sparc] Add support for parsing memory operands in sparc AsmParser.Venkatraman Govindaraju2014-01-071-47/+119
| | | | llvm-svn: 198658
* [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.Venkatraman Govindaraju2014-01-044-0/+655
llvm-svn: 198484
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