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authorCraig Topper <craig.topper@gmail.com>2014-06-18 05:05:13 +0000
committerCraig Topper <craig.topper@gmail.com>2014-06-18 05:05:13 +0000
commit2a30d7889fc54c8a74d73b79be3dd030bac41b06 (patch)
tree2e930ab7dd12150c6d0809b193b24f5618beeb2c /llvm/lib/Target/Sparc/AsmParser
parentf29276edb7b9c85c9f521eb3e301259bee17aa33 (diff)
downloadbcm5719-llvm-2a30d7889fc54c8a74d73b79be3dd030bac41b06.tar.gz
bcm5719-llvm-2a30d7889fc54c8a74d73b79be3dd030bac41b06.zip
Replace some assert(0)'s with llvm_unreachable.
llvm-svn: 211141
Diffstat (limited to 'llvm/lib/Target/Sparc/AsmParser')
-rw-r--r--llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 79075b06bdc..9df00540189 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -330,7 +330,7 @@ public:
unsigned Reg = Op.getReg();
unsigned regIdx = 0;
switch (Op.Reg.Kind) {
- default: assert(0 && "Unexpected register kind!");
+ default: llvm_unreachable("Unexpected register kind!");
case rk_FloatReg:
regIdx = Reg - Sparc::F0;
if (regIdx % 4 || regIdx > 31)
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