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path: root/llvm/lib/Target/RISCV
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* [RISCV] Support assembling TLS add and associated modifiersLewis Revill2019-04-049-11/+202
* Test commit: Remove double variable assignmentLewis Revill2019-04-031-1/+1
* [RISCV] Support assembling @plt symbol operandsAlex Bradbury2019-04-028-6/+34
* [RISCV] Attach VK_RISCV_CALL to symbols upon creationAlex Bradbury2019-04-016-9/+57
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-016-35/+110
* [RISCV] Add seto pattern expansionLuis Marques2019-04-013-3/+11
* [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to lin...Alex Bradbury2019-04-012-2/+21
* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float...Alex Bradbury2019-03-303-17/+128
* [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))Alex Bradbury2019-03-301-0/+11
* [RISCV] Improve codegen for icmp {ne,eq} with a constantLuis Marques2019-03-261-0/+4
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-229-15/+67
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-221-17/+90
* [RISCV] Allow conversion of CC logic to bitwise logicAlex Bradbury2019-03-221-0/+4
* [RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cppAlex Bradbury2019-03-171-11/+17
* [RISCV] Fix RISCVAsmParser::ParseRegister and add testsAlex Bradbury2019-03-171-5/+7
* [RISCV] Fix rL356123Alex Bradbury2019-03-141-2/+2
* [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCV...Alex Bradbury2019-03-142-7/+10
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-131-1/+3
* [RISCV] Replace incorrect use of sizeof with array_lengthofAlex Bradbury2019-03-131-3/+3
* [RISCV][MC] Find matching pcrel_hi fixup in more cases.Eli Friedman2019-03-121-4/+12
* [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64AAlex Bradbury2019-03-111-0/+4
* [RISCV] Allow fp as an alias of s0Alex Bradbury2019-03-111-1/+1
* [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()Alex Bradbury2019-03-112-4/+4
* [RISCV][NFC] Minor refactoring of CC_RISCVAlex Bradbury2019-03-091-7/+7
* [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserterAlex Bradbury2019-03-091-16/+19
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-0910-15/+131
* [RISCV] Allow access to FP CSRs without F extensionAna Pazos2019-03-081-2/+0
* [RISCV][NFC] IsEligibleForTailCallOptimization -> isEligibleForTailCallOptimi...Alex Bradbury2019-02-212-9/+8
* [RISCV] Add implied zero offset load/store alias patternsAlex Bradbury2019-02-214-0/+81
* [RISCV] Implement pseudo instructions for load/store from a symbol address.Kito Cheng2019-02-205-14/+137
* [RISCV][NFC] Move some std::string to StringRefAlex Bradbury2019-02-193-5/+5
* [RISCV] Add assembler support for LA pseudo-instructionAlex Bradbury2019-02-152-18/+76
* [RISCV] Support assembling %got_pcrel_hi operatorAlex Bradbury2019-02-158-8/+32
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-012-4/+30
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-313-2/+130
* [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when...Shiva Chen2019-01-304-1/+70
* [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FDAlex Bradbury2019-01-251-3/+28
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-253-3/+18
* [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64MAlex Bradbury2019-01-253-49/+55
* [RISCV] Custom-legalise 32-bit variable shifts on RV64Alex Bradbury2019-01-253-67/+105
* Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"Ana Pazos2019-01-243-18/+3
* [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-243-3/+18
* [RISCV] Set isReMaterializable for ORI, XORIAna Pazos2019-01-241-0/+4
* Fixed isReMaterializable setting for LUI instruction.Ana Pazos2019-01-221-1/+2
* Reapply "IR: Add fp operations to atomicrmw"Matt Arsenault2019-01-221-0/+6
* [RISCV][NFC] Change naming scheme for RISC-V specific DAG nodesAlex Bradbury2019-01-221-43/+50
* [RISCV] Quick fix for PR40333Alex Bradbury2019-01-221-1/+5
* Revert r351778: IR: Add fp operations to atomicrmwChandler Carruth2019-01-221-6/+0
* [RISCV][NFC] Add break to case statement in RISCVDAGToDAGISel::SelectAlex Bradbury2019-01-221-0/+1
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