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path: root/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
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* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-271-10/+1
| | | | | | | | | | | | | | | | 1. if users don't specific -mattr, the default target-feature come from IR attribute. 2. fixed bug and re-land this patch Reviewers: lenary, asb Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D70837 (cherry picked from commit 0cb274de397a193fb37c60653b336d48a3a4f1bd)
* Revert "[RISCV] Support ABI checking with per function target-features"Zakk Chen2020-01-271-1/+10
| | | | | | | This reverts commit 7bc58a779aaa1de56fad8b1bc8e46932d2f2f1e4. It breaks EXPENSIVE_CHECKS on Windows (cherry picked from commit cef838e65f9a2aeecf5e19431077bc16b01a79fb)
* [RISCV] Check the target-abi module flag matches the optionZakk Chen2020-01-271-10/+14
| | | | | | | | | | | | Reviewers: lenary, asb Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D72768 (cherry picked from commit 1256d68093ac1696034e385bbb4cb6e516b66bea)
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-151-10/+1
| | | | | | | | | | | | | if users don't specific -mattr, the default target-feature come from IR attribute. Reviewers: lenary, asb Reviewed By: lenary, asb Tags: #llvm Differential Revision: https://reviews.llvm.org/D70837
* Revert "[RISCV] Support ABI checking with per function target-features"Zakk Chen2020-01-151-1/+10
| | | | This reverts commit 109e4d12edda07bdec139de36d9fdb6f73399f92.
* [RISCV] Support ABI checking with per function target-featuresZakk Chen2020-01-151-10/+1
| | | | | if users don't specific -mattr, the default target-feature come from IR attribute.
* [RISCV] Handle variable sized objects with the stack need to be realignedShiva Chen2019-11-161-0/+6
| | | | Differential Revision: https://reviews.llvm.org/D68979
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-221-10/+30
| | | | | | | | | | | | | | | | | | | | | The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E. Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC). Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches. Differential Revision: https://reviews.llvm.org/D59470 llvm-svn: 356744
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-091-0/+51
| | | | | | | | | | | | | | | | This patch adds proper handling of -target-abi, as accepted by llvm-mc and llc. Lowering (codegen) for the hard-float ABIs will follow in a subsequent patch. However, this patch does add MC layer support for the hard float and RVE ABIs (emission of the appropriate ELF flags https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-file-header). ABI parsing must be shared between codegen and the MC layer, so we add computeTargetABI to RISCVUtils. A warning will be printed if an invalid or unrecognized ABI is given. Differential Revision: https://reviews.llvm.org/D59023 llvm-svn: 355771
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-0/+9
Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
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