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path: root/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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* [RISCV] Add machine function pass to merge base + offsetSameer AbuAsal2018-06-271-0/+5
* [RISCV] Codegen support for atomic operations on RV32IAlex Bradbury2018-06-131-0/+6
* [RISCV] Use init_array instead of ctors for RISCV target, by defaultMandeep Singh Grang2018-03-241-1/+2
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-101-0/+3
* [RISCV] Fix 64-bit data layout mismatch between backend and target descriptionMandeep Singh Grang2017-11-161-1/+1
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-2/+24
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-121-3/+3
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-121-3/+3
* Delete Default and JITDefault code modelsRafael Espindola2017-08-031-3/+10
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFCMatthias Braun2017-05-301-1/+1
* [RISCV] Fix RV32 datalayout string and ensure initAsmInfo is calledAlex Bradbury2017-02-141-2/+4
* [RISCV] Add stub backendAlex Bradbury2016-11-011-0/+58
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