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path: root/llvm/lib/Target/RISCV/RISCVSubtarget.h
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-221-0/+5
* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-0/+1
* Revert Patch from PhabricatorLuis Marques2019-09-171-1/+0
* Patch from PhabricatorLuis Marques2019-09-171-0/+1
* [RISCV] Add support for RVC HINT instructionsLuis Marques2019-08-211-0/+2
* [RISCV GlobalISel] Adding initial GlobalISel infrastructureDaniel Sanders2019-08-201-0/+17
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-221-0/+2
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-091-3/+7
* [RISCV][NFC] Move some std::string to StringRefAlex Bradbury2019-02-191-2/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen2018-05-151-0/+2
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-0/+2
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+2
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+2
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-1/+3
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-091-0/+2
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+75
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