| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Add codegen for RV32F floating point load/store | Alex Bradbury | 2018-03-20 | 1 | -0/+3 |
| * | [RISCV] Implement support for the BranchRelaxation pass | Alex Bradbury | 2018-01-10 | 1 | -4/+4 |
| * | [RISCV] Support and tests for a variety of additional LLVM IR constructs | Alex Bradbury | 2017-11-21 | 1 | -0/+8 |
| * | [RISCV] Initial support for function calls | Alex Bradbury | 2017-11-08 | 1 | -0/+3 |
| * | [RISCV] Codegen for conditional branches | Alex Bradbury | 2017-11-08 | 1 | -0/+4 |
| * | [RISCV] Codegen support for memory operations on global addresses | Alex Bradbury | 2017-11-08 | 1 | -18/+58 |
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -0/+50 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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