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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-2/+4
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-0/+1
* [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury2018-04-261-0/+49
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-0/+2
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-2/+11
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-11/+2
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-121-7/+11
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-121-0/+4
* [RISCV] Codegen support for RV32F floating point comparison operationsAlex Bradbury2018-03-211-10/+31
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-101-5/+110
* [RISCV] Implement branch analysisAlex Bradbury2018-01-101-0/+166
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-0/+20
* [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/lo...Alex Bradbury2017-12-071-2/+2
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-1/+2
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+33
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+12
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+31
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