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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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* [RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury2018-01-021-2/+1
| | | | | | XLenVT in LowerFormalArguments is used only in an assert. llvm-svn: 321642
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-111-33/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
| | | | llvm-svn: 320358
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-15/+91
| | | | | | | | | | | | | | | | | | | | | | Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-211-0/+152
| | | | | | | | | | | | | | Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and ultimately the integer RISC-V conditional branch instructions), we choose to expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch will be created in the case where an ISD::SELECT condition value is created by an ISD::SETCC node, which operates on XLen types. Other datatypes such as floating point don't have conditional branch instructions, and lowering ISD::SELECT allows more flexibility for handling these cases. Differential Revision: https://reviews.llvm.org/D29937 llvm-svn: 318735
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-0/+132
| | | | | | | | | Note that this is just enough for simple function call examples to generate working code. Support for varargs etc follows in future patches. Differential Revision: https://reviews.llvm.org/D29936 llvm-svn: 317691
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+1
| | | | | | | | | | | | | | | | | | | | A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex. Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form. I had to change simm13_lsb0 and simm21_lsb0 to inherit from the Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!). Differential Revision: https://reviews.llvm.org/D29935 llvm-svn: 317690
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-081-0/+25
| | | | | | Differential Revision: https://reviews.llvm.org/D39103 llvm-svn: 317688
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+3
| | | | | | | | | This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support for lowering global addresses follow in the next patch. Differential Revision: https://reviews.llvm.org/D29934 llvm-svn: 317685
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+170
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
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