summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Rename FPRs and use Register arithmeticLuis Marques2019-09-271-36/+38
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-1/+1
* [RISCV] Fix static analysis issuesLuis Marques2019-09-201-2/+1
* [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignmentGuillaume Chatelet2019-09-061-2/+2
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-3/+3
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-2/+2
* [RISCV] Enable tail call opt for variadic functionJim Lin2019-09-041-5/+0
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-281-0/+10
* Do a sweep of symbol internalization. NFC.Benjamin Kramer2019-08-231-2/+2
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-161-12/+12
* [RISCV] Lower inline asm constraint A for RISC-VLewis Revill2019-08-161-0/+17
* [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-18/+18
* [RISCV] Fix ICE in isDesirableToCommuteWithShiftSam Elliott2019-08-121-2/+4
* [RISCV] Allow ABI Names in Inline Assembly ConstraintsSam Elliott2019-08-081-34/+78
* [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensionsShiva Chen2019-08-061-0/+24
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-1/+1
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-031-0/+4
* [RISCV] Support 'f' Inline Assembly ConstraintSam Elliott2019-07-311-0/+21
* [RISCV] Add support for lowering floating point inlineasm clobbersSimon Cook2019-07-311-0/+46
* [RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudoAlex Bradbury2019-07-181-0/+1
* [RISCV] Fix ICE in isDesirableToCommuteWithShiftSam Elliott2019-07-091-1/+1
* [RISCV] Specify registers used in DWARF exception handlingAlex Bradbury2019-07-081-0/+10
* [RISCV] Support @llvm.readcyclecounter() IntrinsicSam Elliott2019-07-051-0/+86
* [RISCV] Add lowering of global TLS addressesLewis Revill2019-06-191-0/+114
* [RISCV] Prevent re-ordering some adds after shiftsSam Elliott2019-06-181-0/+45
* [RISCV] Lower calls through PLTLewis Revill2019-06-181-4/+14
* [RISCV] Add lowering of addressing sequences for PICLewis Revill2019-06-111-11/+19
* [RISCV] Lower inline asm constraints I, J & K for RISC-VLewis Revill2019-06-111-0/+38
* [RISCV] Support Bit-Preserving FP in F/D ExtensionsSam Elliott2019-06-071-0/+5
* [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTSLuis Marques2019-04-161-3/+100
* Test commit: Remove double variable assignmentLewis Revill2019-04-031-1/+1
* [RISCV] Attach VK_RISCV_CALL to symbols upon creationAlex Bradbury2019-04-011-2/+4
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-011-35/+53
* [RISCV] Add seto pattern expansionLuis Marques2019-04-011-3/+3
* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float...Alex Bradbury2019-03-301-15/+92
* [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))Alex Bradbury2019-03-301-0/+11
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-221-0/+3
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-221-17/+90
* [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()Alex Bradbury2019-03-111-2/+2
* [RISCV][NFC] Minor refactoring of CC_RISCVAlex Bradbury2019-03-091-7/+7
* [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserterAlex Bradbury2019-03-091-16/+19
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-091-0/+6
* [RISCV][NFC] IsEligibleForTailCallOptimization -> isEligibleForTailCallOptimi...Alex Bradbury2019-02-211-6/+5
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-011-4/+7
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-311-1/+74
* [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FDAlex Bradbury2019-01-251-3/+28
* [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64MAlex Bradbury2019-01-251-30/+28
* [RISCV] Custom-legalise 32-bit variable shifts on RV64Alex Bradbury2019-01-251-32/+86
* Reapply "IR: Add fp operations to atomicrmw"Matt Arsenault2019-01-221-0/+6
* [RISCV] Quick fix for PR40333Alex Bradbury2019-01-221-1/+5
OpenPOWER on IntegriCloud