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* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+43
| | | | | | | | | | | | | | | | | | | | | - Save/restore only registers that are used. This includes Callee saved registers and Caller saved registers (arguments and temporaries) for integer and FP registers. - If there is a call in the interrupt handler, save/restore all Caller saved registers (arguments and temporaries) and all FP registers. - Emit special return instructions depending on "interrupt" attribute type. Based on initial patch by Zhaoshi Zheng. Reviewers: asb Reviewed By: asb Subscribers: rkruppe, the_o, MartinMosbeck, brucehoult, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, llvm-commits Differential Revision: https://reviews.llvm.org/D48411 llvm-svn: 338047
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-131-2/+22
| | | | | | | | | | | | | | | Fences are inserted according to table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Instruction selection failures will now occur for 8/16/32-bit atomicrmw and cmpxchg operations when targeting RV32IA until lowering for these operations is added in a follow-on patch. Differential Revision: https://reviews.llvm.org/D47589 llvm-svn: 334591
* [RISCV] Codegen support for atomic operations on RV32IAlex Bradbury2018-06-131-0/+3
| | | | | | | | | | | | | | | | | This patch adds lowering for atomic fences and relies on AtomicExpandPass to lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls. test/CodeGen/RISCV/atomic-* are modelled on the exhaustive test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A codegen support is introduced. Fence mappings are taken from table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Differential Revision: https://reviews.llvm.org/D47587 llvm-svn: 334590
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-5/+0
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-8/+117
| | | | | | | This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-171-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-4/+4
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-0/+14
| | | | | | | This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected and avoiding unnecessary masks. llvm-svn: 330943
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-261-0/+20
| | | | | | Adapted from ARM's implementation introduced in r313533 and r314280. llvm-svn: 330940
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-261-0/+4
| | | | | | | | I'm unable to construct a representative test case that demonstrates the advantage, but it seems sensible to report accurate target-specific information regardless. llvm-svn: 330938
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-261-0/+4
| | | | | | | This causes a trivial improvement in the recently added lsr-legaladdimm.ll test case. llvm-svn: 330937
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-261-0/+26
| | | | | | | | | | | | This has no impact on codegen for the current RISC-V unit tests or my small benchmark set and very minor changes in a few programs in the GCC torture suite. Based on this, I haven't been able to produce a representative test program that demonstrates a benefit from isLegalAddressingMode. I'm committing the patch anyway, on the basis that presenting accurate information to the target-independent code is preferable to relying on incorrect generic assumptions. llvm-svn: 330932
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-4/+7
| | | | | | | | | | | | | | | | To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
* [RISCV] Fix assert message operatorMandeep Singh Grang2018-04-161-1/+1
| | | | | | | | | | | | | | | | Summary: Specifying assert message with an || operator makes the compiler interpret it as a bool. Changed it to &&. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits Differential Revision: https://reviews.llvm.org/D45660 llvm-svn: 330148
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-2/+3
| | | | | | | | | | | | | | | | | | Summary: According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but instruction allow to be aligned to 16-bit boundaries for C-extension. So we just align to 4 bytes and 2 bytes for C-extension is enough. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D45560 Patch by Kito Cheng. llvm-svn: 329899
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-121-4/+12
| | | | | | | | Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-121-0/+1
| | | | | | | This also includes support and a test for truncating stores, which are now possible thanks to the fpround pattern. llvm-svn: 329876
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-121-1/+4
| | | | llvm-svn: 329874
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ↵Alex Bradbury2018-04-121-17/+214
| | | | | | | | | | | | | | | | conv fadd.d is required in order to force floating point registers to be used in test code, as parameters are passed in integer registers in the soft float ABI. Much of this patch is concerned with support for passing f64 on RV32D with a soft-float ABI. Similar to Mips, introduce pseudoinstructions to build an f64 out of a pair of i32 and to split an f64 to a pair of i32. BUILD_PAIR and EXTRACT_ELEMENT can't be used, as a BITCAST to i64 would be necessary, but i64 is not a legal type. llvm-svn: 329871
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to ↵Craig Topper2018-03-291-1/+1
| | | | | | | | | | | | CodeGen layer. Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it. The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly. Differential Revision: https://reviews.llvm.org/D45017 llvm-svn: 328806
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
| | | | | | ValueTypes.h is implemented in IR already. llvm-svn: 328397
* [RISCV] Codegen support for RV32F floating point comparison operationsAlex Bradbury2018-03-211-2/+15
| | | | | | | | | This patch also includes extensive tests targeted at select and br+fcmp IR inputs. A sequence of br+fcmp required support for FPR32 registers to be added to RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot. llvm-svn: 328104
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-201-0/+26
| | | | | | | As part of this, add support for load/store from the constant pool. This is used to materialise f32 constants. llvm-svn: 327979
* [RISCV] Add codegen for RV32F arithmetic and conversion operationsAlex Bradbury2018-03-201-5/+48
| | | | | | Currently, only a soft floating point ABI is supported. llvm-svn: 327976
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-021-0/+7
| | | | | | | | To avoid trigger "No default SetCC type for vectors!" Assertion Differential Revision: https://reviews.llvm.org/D42675 llvm-svn: 324054
* [RISCV] Codegen support for the standard RV32M instruction set extensionAlex Bradbury2018-01-181-8/+10
| | | | llvm-svn: 322843
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-101-0/+57
| | | | llvm-svn: 322218
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+18
| | | | llvm-svn: 322217
* [RISCV] Support for varargsAlex Bradbury2018-01-101-20/+125
| | | | | | | | | | | | Includes support for expanding va_copy. Also adds support for using 'aligned' registers when necessary for vararg calls, and ensure the frame pointer always points to the bottom of the vararg spill region. This is necessary to ensure that the saved return address and stack pointer are always available at fixed known offsets of the frame pointer. Differential Revision: https://reviews.llvm.org/D40805 llvm-svn: 322215
* [RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury2018-01-021-2/+1
| | | | | | XLenVT in LowerFormalArguments is used only in an assert. llvm-svn: 321642
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-111-33/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
| | | | llvm-svn: 320358
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-15/+91
| | | | | | | | | | | | | | | | | | | | | | Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-211-0/+152
| | | | | | | | | | | | | | Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and ultimately the integer RISC-V conditional branch instructions), we choose to expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch will be created in the case where an ISD::SELECT condition value is created by an ISD::SETCC node, which operates on XLen types. Other datatypes such as floating point don't have conditional branch instructions, and lowering ISD::SELECT allows more flexibility for handling these cases. Differential Revision: https://reviews.llvm.org/D29937 llvm-svn: 318735
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-0/+132
| | | | | | | | | Note that this is just enough for simple function call examples to generate working code. Support for varargs etc follows in future patches. Differential Revision: https://reviews.llvm.org/D29936 llvm-svn: 317691
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+1
| | | | | | | | | | | | | | | | | | | | A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex. Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form. I had to change simm13_lsb0 and simm21_lsb0 to inherit from the Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!). Differential Revision: https://reviews.llvm.org/D29935 llvm-svn: 317690
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-081-0/+25
| | | | | | Differential Revision: https://reviews.llvm.org/D39103 llvm-svn: 317688
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+3
| | | | | | | | | This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support for lowering global addresses follow in the next patch. Differential Revision: https://reviews.llvm.org/D29934 llvm-svn: 317685
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+170
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
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