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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+43
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-131-2/+22
* [RISCV] Codegen support for atomic operations on RV32IAlex Bradbury2018-06-131-0/+3
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-5/+0
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-8/+117
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-171-5/+10
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-4/+4
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-0/+14
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-261-0/+20
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-261-0/+4
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-261-0/+4
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-261-0/+26
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-4/+7
* [RISCV] Fix assert message operatorMandeep Singh Grang2018-04-161-1/+1
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-2/+3
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-121-4/+12
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-121-0/+1
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-121-1/+4
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-121-17/+214
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* [RISCV] Codegen support for RV32F floating point comparison operationsAlex Bradbury2018-03-211-2/+15
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-201-0/+26
* [RISCV] Add codegen for RV32F arithmetic and conversion operationsAlex Bradbury2018-03-201-5/+48
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-021-0/+7
* [RISCV] Codegen support for the standard RV32M instruction set extensionAlex Bradbury2018-01-181-8/+10
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-101-0/+57
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+18
* [RISCV] Support for varargsAlex Bradbury2018-01-101-20/+125
* [RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury2018-01-021-2/+1
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-111-33/+361
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-15/+91
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-211-0/+152
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-0/+132
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+1
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-081-0/+25
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+3
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+170
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