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path: root/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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* [RISCV] Allow shrink wrapping for RISC-Vlewis-revill2020-01-141-4/+16
* [RISCV] Handle variable sized objects with the stack need to be realignedShiva Chen2019-11-161-11/+27
* [RISCV] Fix wrong CFI directivesLuís Marques2019-11-141-55/+0
* Revert "[RISCV] Fix wrong CFI directives"Luís Marques2019-11-131-0/+55
* [RISCV] Fix wrong CFI directivesLuís Marques2019-11-131-55/+0
* [RISCV] Fix CFA when doing split sp adjustment with fpLuís Marques2019-11-101-15/+25
* [RISCV][NFC] Add CFI-related testsLuís Marques2019-11-101-0/+2
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-221-0/+11
* [RISCV] Split SP adjustment to reduce the offset of callee saved register spi...Shiva Chen2019-10-041-1/+85
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-4/+2
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-131-2/+4
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-4/+2
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-161-12/+12
* [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-2/+2
* [RISCV] Minimal stack realignment supportSam Elliott2019-08-081-2/+46
* [RISCV] Add CFI directives for RISCV prologue/epilog.Hsiangkai Wang2019-06-121-3/+70
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Fix std::advance slownessAna Pazos2018-08-241-2/+1
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+30
* [RISCV] Preserve stack space for outgoing arguments when the function contain...Shiva Chen2018-03-201-15/+36
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-19/+22
* [RISCV] Reserve an emergency spill slot for the register scavenger when neces...Alex Bradbury2018-01-111-0/+19
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-7/+23
* [RISCV] Support for varargsAlex Bradbury2018-01-101-3/+12
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-111-2/+145
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-0/+29
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+29
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