Commit message (Expand) | Author | Age | Files | Lines | |
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* | Revert "[RISCV] implement li pseudo instruction" | Alex Bradbury | 2018-04-18 | 1 | -9/+0 |
* | [RISCV] implement li pseudo instruction | Alex Bradbury | 2018-04-17 | 1 | -0/+9 |
* | [RISCV] Tablegen-driven Instruction Compression. | Sameer AbuAsal | 2018-04-06 | 1 | -0/+11 |
* | [RISCV] Add basic support for inline asm constraints | Alex Bradbury | 2018-01-10 | 1 | -0/+55 |
* | [RISCV] Codegen support for memory operations on global addresses | Alex Bradbury | 2017-11-08 | 1 | -1/+6 |
* | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -0/+67 |